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Update Instruction Set

zxq5
2025-06-18 15:23:36 +01:00
parent a6a25d0ca2
commit 983189cedf
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Instruction-Set.md
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@@ -84,8 +84,8 @@ See the Pseduo-Instructions reference in [Assembler](https://git.zxq5.dev/LowLev
| 0x14 | R | CMP | Reg1, Reg2 | Compares the value of Reg1 to the value in Reg2. The results of the comparisons are set in the Status register. |
| 0x15 | R | INC | Reg | Increments the value in the given register. |
| 0x16 | R | DEC | Reg | Decrements the value in the given register. |
| 0x17 | I | SHL | Reg, Literal \| ValReg | Left shifts the value in Reg by the given amount (either a register, or a literal value). |
| 0x18 | I | SHR | Reg, Literal \| ValReg | Right shifts the value in Reg by the given amount (either a register, or a literal value). |
| 0x17 | R | SHL | Reg, Literal \| ValReg | Left shifts the value in Reg by the given amount (either a register, or a literal value). |
| 0x18 | R | SHR | Reg, Literal \| ValReg | Right shifts the value in Reg by the given amount (either a register, or a literal value). |
| 0x19 | R | ADD | Src1, Src2, Dest | Adds the value of Src2 to Src1 and writes the result to Dest. |
| 0x1A | R | SUB | Src1, Src2, Dest | Subtracts the value of Src2 from Src1 and writes the result to Dest. |
| 0x1B | R | AND | Src1, Src2, Dest | Performs bitwise AND on Src1 and Src2 storing the result in Dest. |