398 lines
22 KiB
HTML
398 lines
22 KiB
HTML
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<main>
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<h1 id="hardware-instructions"><a class="header" href="#hardware-instructions">Hardware Instructions</a></h1>
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<h3 id="data-movement-instructions"><a class="header" href="#data-movement-instructions">Data Movement Instructions</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>MOV</strong></td><td><code>src_reg, dest_reg</code></td><td>Copy value from source to destination register</td></tr>
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<tr><td><strong>MOVS</strong></td><td><code>src_reg, dest_reg</code></td><td>Copy with sign extension</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">mov rg0, rg1 ; Copy rg0 to rg1
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movs rg0, rg1 ; Copy rg0 to rg1 with sign extension
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</code></pre>
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<h3 id="memory-access-instructions"><a class="header" href="#memory-access-instructions">Memory Access Instructions</a></h3>
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<h4 id="load-instructions"><a class="header" href="#load-instructions">Load Instructions</a></h4>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>LDB</strong></td><td><code>base_reg, dest_reg [, offset]</code><br><code>label, dest_reg [, offset]</code></td><td>Load byte from memory</td></tr>
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<tr><td><strong>LDBS</strong></td><td><code>base_reg, dest_reg [, offset]</code><br><code>label, dest_reg [, offset]</code></td><td>Load byte with sign extension</td></tr>
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<tr><td><strong>LDH</strong></td><td><code>base_reg, dest_reg [, offset]</code><br><code>label, dest_reg [, offset]</code></td><td>Load half-word (16-bit)</td></tr>
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<tr><td><strong>LDHS</strong></td><td><code>base_reg, dest_reg [, offset]</code><br><code>label, dest_reg [, offset]</code></td><td>Load half-word with sign extension</td></tr>
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<tr><td><strong>LDW</strong></td><td><code>base_reg, dest_reg [, offset]</code><br><code>label, dest_reg [, offset]</code></td><td>Load word (32-bit)</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">; Direct register addressing
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ldb rg0, rg1 ; Load byte from address in rg0
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ldw rg0, rg1, 8 ; Load word from (rg0 + 8)
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; Label addressing
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ldb buffer, rg2 ; Load byte from label 'buffer'
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ldw stack, bpr ; Load stack address into base pointer
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</code></pre>
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<p><strong>Label Expansions:</strong></p>
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<pre><code class="language-dsa">; ldb buffer, rg2 expands to:
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lli buffer, rg2 ; Load lower 16 bits of buffer address
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lui buffer, rg2 ; Load upper 16 bits of buffer address
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ldb rg2, rg2 ; Load byte from address in rg2
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; ldw stack, bpr expands to:
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lli stack, bpr ; Load lower 16 bits of stack address
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lui stack, bpr ; Load upper 16 bits of stack address
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ldw bpr, bpr ; Load word from address in bpr
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</code></pre>
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<h4 id="store-instructions"><a class="header" href="#store-instructions">Store Instructions</a></h4>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>STB</strong></td><td><code>src_reg, base_reg [, offset]</code><br><code>src_reg, label [, offset]</code></td><td>Store byte to memory</td></tr>
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<tr><td><strong>STH</strong></td><td><code>src_reg, base_reg [, offset]</code><br><code>src_reg, label [, offset]</code></td><td>Store half-word to memory</td></tr>
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<tr><td><strong>STW</strong></td><td><code>src_reg, base_reg [, offset]</code><br><code>src_reg, label [, offset]</code></td><td>Store word to memory</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">; Direct register addressing
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stb rg0, rg1 ; Store byte from rg0 to address in rg1
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stw rg0, rg1, 12 ; Store word to (rg1 + 12)
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; Label addressing
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stb acc, buffer ; Store byte from accumulator to 'buffer'
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stw rg1, current ; Store word to 'current' variable
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</code></pre>
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<p><strong>Label Expansions:</strong></p>
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<pre><code class="language-dsa">; stb acc, buffer expands to:
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lli buffer, rgf ; Load lower 16 bits of buffer address
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lui buffer, rgf ; Load upper 16 bits of buffer address
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stb acc, rgf ; Store byte from acc to address in rgf
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; stw rg1, current expands to:
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lli current, rgf ; Load lower 16 bits of current address
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lui current, rgf ; Load upper 16 bits of current address
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stw rg1, rgf ; Store word from rg1 to address in rgf
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</code></pre>
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<h3 id="immediate-load-instructions"><a class="header" href="#immediate-load-instructions">Immediate Load Instructions</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>LLI</strong></td><td><code>imm, dest_reg</code></td><td>Load 16-bit immediate into lower 16 bits<br/><strong>Clears upper 16 bits!</strong></td></tr>
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<tr><td><strong>LUI</strong></td><td><code>imm, dest_reg</code></td><td>Load 16-bit immediate into upper 16 bits</td></tr>
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</tbody></table>
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</div>
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<p><strong>Usage</strong></p>
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<p>ensure that you always run <strong>Lli</strong> before <strong>Lui</strong> as <strong>Lli</strong> clears the upper 16 bits.</p>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">lli 0x1234, rg0 ; Load 0x1234 into lower 16 bits of rg0
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lui 0xABCD, rg0 ; Load 0xABCD into upper 16 bits of rg0
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</code></pre>
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<h3 id="jump-instructions"><a class="header" href="#jump-instructions">Jump Instructions</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>JMP</strong></td><td><code>addr [, offset_reg]</code><br><code>imm, offset_reg</code></td><td>Unconditional jump</td></tr>
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<tr><td><strong>JEQ</strong></td><td><code>addr [, offset_reg]</code></td><td>Jump if equal flag set</td></tr>
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<tr><td><strong>JNE</strong></td><td><code>addr [, offset_reg]</code></td><td>Jump if not equal flag set</td></tr>
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<tr><td><strong>JGT</strong></td><td><code>addr [, offset_reg]</code></td><td>Jump if greater than flag set</td></tr>
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<tr><td><strong>JGE</strong></td><td><code>addr [, offset_reg]</code></td><td>Jump if greater or equal flags set</td></tr>
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<tr><td><strong>JLT</strong></td><td><code>addr [, offset_reg]</code></td><td>Jump if less than flag set</td></tr>
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<tr><td><strong>JLE</strong></td><td><code>addr [, offset_reg]</code></td><td>Jump if less or equal flags set</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">jmp start ; Jump to label 'start'
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jmp 4, ret ; Jump to address (4 + ret register)
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jeq end ; Jump to 'end' if equal flag set
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jgt loop ; Jump to 'loop' if greater than flag set
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</code></pre>
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<h3 id="arithmetic-instructions"><a class="header" href="#arithmetic-instructions">Arithmetic Instructions</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>ADD</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Addition</td></tr>
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<tr><td><strong>SUB</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Subtraction</td></tr>
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<tr><td><strong>IADD</strong></td><td><code>src_reg, imm [, dest_reg]</code></td><td>Immediate addition</td></tr>
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<tr><td><strong>ISUB</strong></td><td><code>src_reg, imm [, dest_reg]</code></td><td>Immediate subtraction</td></tr>
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<tr><td><strong>INC</strong></td><td><code>reg</code></td><td>Increment register by 1</td></tr>
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<tr><td><strong>DEC</strong></td><td><code>reg</code></td><td>Decrement register by 1</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">add rg0, rg1, rg2 ; rg2 = rg0 + rg1
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sub rg0, rg1, rg2 ; rg2 = rg0 - rg1
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iadd rg0, 10 ; rg0 = rg0 + 10
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// or using alternate syntax
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addi rg0, 1 ; rg0 = rg0 + 1
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inc rg0 ; rg0 = rg0 + 1
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</code></pre>
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<h3 id="bitwise-operations"><a class="header" href="#bitwise-operations">Bitwise Operations</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>AND</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Bitwise AND</td></tr>
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<tr><td><strong>OR</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Bitwise OR</td></tr>
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<tr><td><strong>XOR</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Bitwise XOR</td></tr>
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<tr><td><strong>NOT</strong></td><td><code>src_reg, dest_reg</code></td><td>Bitwise NOT</td></tr>
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<tr><td><strong>NAND</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Bitwise NAND</td></tr>
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<tr><td><strong>NOR</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Bitwise NOR</td></tr>
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<tr><td><strong>XNOR</strong></td><td><code>src1_reg, src2_reg, dest_reg</code></td><td>Bitwise XNOR</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">and rg0, rg1, rg2 ; rg2 = rg0 & rg1
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not rg0, rg1 ; rg1 = ~rg0
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</code></pre>
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<h3 id="shift-operations"><a class="header" href="#shift-operations">Shift Operations</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>SHL</strong></td><td><code>reg, shift_amount</code></td><td>Shift left</td></tr>
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<tr><td><strong>SHR</strong></td><td><code>reg, shift_amount</code></td><td>Shift right</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">shl rg0, 2 ; Shift rg0 left by 2 bits
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shr rg0, 3 ; Shift rg0 right by 3 bits
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</code></pre>
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<h3 id="comparison-and-control"><a class="header" href="#comparison-and-control">Comparison and Control</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>CMP</strong></td><td><code>reg1, reg2</code></td><td>Compare registers and set flags</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">cmp rg0, zero ; Compare rg0 with zero register
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cmp rg1, rg2 ; Compare rg1 with rg2
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</code></pre>
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<h3 id="system-instructions"><a class="header" href="#system-instructions">System Instructions</a></h3>
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<div class="table-wrapper"><table><thead><tr><th>Mnemonic</th><th>Operands</th><th>Description</th></tr></thead><tbody>
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<tr><td><strong>HLT</strong></td><td>-</td><td>Halt processor execution</td></tr>
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<tr><td><strong>NOP</strong></td><td>-</td><td>No operation</td></tr>
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<tr><td><strong>INT</strong></td><td><code>interrupt_code</code></td><td>Trigger interrupt</td></tr>
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<tr><td><strong>IRT</strong></td><td>-</td><td>Return from interrupt</td></tr>
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</tbody></table>
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</div>
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<p><strong>Examples:</strong></p>
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<pre><code class="language-dsa">hlt ; Stop processor execution
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int 0x21 ; Trigger interrupt 0x21
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</code></pre>
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</main>
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