common: add tests and opcode method
This commit is contained in:
+92
-40
@@ -154,69 +154,121 @@ impl std::fmt::Display for Register {
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}
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}
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#[derive(Debug, Clone)]
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#[derive(Debug, Clone, Copy)]
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#[repr(u8)]
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pub enum Instruction {
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// No-op
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Nop,
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Nop = 0x0,
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// Data transfer instructions
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Mov(Register, Register),
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MovSigned(Register, Register),
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Mov(Register, Register) = 0x1,
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MovSigned(Register, Register) = 0x2,
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LoadByte(Register, Offset, Register),
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LoadByteSigned(Register, Offset, Register),
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LoadHalfword(Register, Offset, Register),
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LoadHalfwordSigned(Register, Offset, Register),
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LoadWord(Register, Offset, Register),
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LoadByte(Register, Offset, Register) = 0x3,
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LoadByteSigned(Register, Offset, Register) = 0x4,
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LoadHalfword(Register, Offset, Register) = 0x5,
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LoadHalfwordSigned(Register, Offset, Register) = 0x6,
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LoadWord(Register, Offset, Register) = 0x7,
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StoreByte(Register, Offset, Register),
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StoreHalfword(Register, Offset, Register),
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StoreWord(Register, Offset, Register),
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StoreByte(Register, Offset, Register) = 0x8,
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StoreHalfword(Register, Offset, Register) = 0x9,
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StoreWord(Register, Offset, Register) = 0xA,
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LoadLowerImmediate(Register, Immediate),
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LoadUpperImmediate(Register, Immediate),
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LoadLowerImmediate(Register, Immediate) = 0xB,
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LoadUpperImmediate(Register, Immediate) = 0xC,
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// Jump Instructions
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Jump(Register, Offset),
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JumpEq(Register, Offset),
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JumpNeq(Register, Offset),
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JumpGt(Register, Offset),
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JumpGe(Register, Offset),
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JumpLt(Register, Offset),
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JumpLe(Register, Offset),
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Jump(Register, Offset) = 0xD,
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JumpEq(Register, Offset) = 0xE,
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JumpNeq(Register, Offset) = 0xF,
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JumpGt(Register, Offset) = 0x10,
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JumpGe(Register, Offset) = 0x11,
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JumpLt(Register, Offset) = 0x12,
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JumpLe(Register, Offset) = 0x13,
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// Comparison
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Compare(Register, Register),
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Compare(Register, Register) = 0x14,
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// Arithmetic
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Add(Register, Register, Register),
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Sub(Register, Register, Register),
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Increment(Register),
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Decrement(Register),
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ShiftLeft(Register, Register, Immediate),
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ShiftRight(Register, Register, Immediate),
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Add(Register, Register, Register) = 0x19,
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Sub(Register, Register, Register) = 0x1A,
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Increment(Register) = 0x15,
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Decrement(Register) = 0x16,
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ShiftLeft(Register, Register, Immediate) = 0x17,
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ShiftRight(Register, Register, Immediate) = 0x18,
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// Logical
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And(Register, Register, Register),
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Or(Register, Register, Register),
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Not(Register, Register),
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Xor(Register, Register, Register),
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Nand(Register, Register, Register),
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Nor(Register, Register, Register),
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Xnor(Register, Register, Register),
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And(Register, Register, Register) = 0x1B,
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Or(Register, Register, Register) = 0x1C,
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Not(Register, Register) = 0x1D,
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Xor(Register, Register, Register) = 0x1E,
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Nand(Register, Register, Register) = 0x1F,
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Nor(Register, Register, Register) = 0x20,
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Xnor(Register, Register, Register) = 0x21,
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// Misc
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Interrupt(Interrupt),
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IntReturn,
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Halt,
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Interrupt(Interrupt) = 0x22,
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IntReturn = 0x23,
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Halt = 0x24,
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}
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impl Instruction {
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/// Returns the opcode of an instruction.
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///
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/// # Notes
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///
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/// The top two bits shall be 0, opcodes are 6-bits long.
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#[must_use]
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pub fn encode(&self) -> u32 {
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todo!("imlement instruction encoding")
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pub const fn opcode(&self) -> u8 {
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unsafe { *std::ptr::from_ref::<Self>(self).cast::<u8>() }
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}
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#[must_use]
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#[allow(unused)]
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pub fn encode(&self) -> u32 {
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match self {
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Self::Nop => todo!(),
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Self::Mov(src, dst) => todo!(),
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Self::MovSigned(register, register1) => todo!(),
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Self::LoadByte(register, _, register1) => todo!(),
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Self::LoadByteSigned(register, _, register1) => todo!(),
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Self::LoadHalfword(register, _, register1) => todo!(),
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Self::LoadHalfwordSigned(register, _, register1) => todo!(),
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Self::LoadWord(register, _, register1) => todo!(),
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Self::StoreByte(register, _, register1) => todo!(),
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Self::StoreHalfword(register, _, register1) => todo!(),
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Self::StoreWord(register, _, register1) => todo!(),
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Self::LoadLowerImmediate(register, _) => todo!(),
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Self::LoadUpperImmediate(register, _) => todo!(),
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Self::Jump(register, _) => todo!(),
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Self::JumpEq(register, _) => todo!(),
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Self::JumpNeq(register, _) => todo!(),
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Self::JumpGt(register, _) => todo!(),
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Self::JumpGe(register, _) => todo!(),
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Self::JumpLt(register, _) => todo!(),
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Self::JumpLe(register, _) => todo!(),
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Self::Compare(register, register1) => todo!(),
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Self::Add(register, register1, register2) => todo!(),
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Self::Sub(register, register1, register2) => todo!(),
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Self::Increment(register) => todo!(),
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Self::Decrement(register) => todo!(),
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Self::ShiftLeft(register, register1, _) => todo!(),
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Self::ShiftRight(register, register1, _) => todo!(),
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Self::And(register, register1, register2) => todo!(),
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Self::Or(register, register1, register2) => todo!(),
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Self::Not(register, register1) => todo!(),
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Self::Xor(register, register1, register2) => todo!(),
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Self::Nand(register, register1, register2) => todo!(),
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Self::Nor(register, register1, register2) => todo!(),
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Self::Xnor(register, register1, register2) => todo!(),
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Self::Interrupt(interrupt) => todo!(),
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Self::IntReturn => todo!(),
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Self::Halt => todo!(),
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}
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}
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const fn _encode_mov() {}
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#[must_use]
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pub const fn decode(_data: u32) -> Self {
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// TODO: this needs to actually decode something
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@@ -1 +1,4 @@
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pub mod instructions;
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#[cfg(test)]
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mod tests;
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@@ -0,0 +1,175 @@
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use crate::common::instructions::*;
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#[test]
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fn test_opcode_basic_instructions() {
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assert_eq!(Instruction::Nop.opcode(), 0x0);
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assert_eq!(Instruction::Mov(Register::Rg0, Register::Rg1).opcode(), 0x1);
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assert_eq!(
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Instruction::MovSigned(Register::Rg0, Register::Rg1).opcode(),
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0x2
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);
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assert_eq!(Instruction::Halt.opcode(), 0x24);
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}
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#[test]
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fn test_opcode_data_transfer_instructions() {
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assert_eq!(
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Instruction::LoadByte(Register::Rg0, 0, Register::Rg1).opcode(),
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0x3
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);
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assert_eq!(
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Instruction::LoadByteSigned(Register::Rg0, 0, Register::Rg1).opcode(),
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0x4
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);
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assert_eq!(
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Instruction::LoadHalfword(Register::Rg0, 0, Register::Rg1).opcode(),
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0x5
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);
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assert_eq!(
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Instruction::LoadHalfwordSigned(Register::Rg0, 0, Register::Rg1).opcode(),
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0x6
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);
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assert_eq!(
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Instruction::LoadWord(Register::Rg0, 0, Register::Rg1).opcode(),
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0x7
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);
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assert_eq!(
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Instruction::StoreByte(Register::Rg0, 0, Register::Rg1).opcode(),
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0x8
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);
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assert_eq!(
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Instruction::StoreHalfword(Register::Rg0, 0, Register::Rg1).opcode(),
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0x9
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);
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assert_eq!(
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Instruction::StoreWord(Register::Rg0, 0, Register::Rg1).opcode(),
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0xA
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);
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}
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#[test]
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fn test_opcode_immediate_instructions() {
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assert_eq!(
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Instruction::LoadLowerImmediate(Register::Rg0, 0).opcode(),
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0xB
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);
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assert_eq!(
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Instruction::LoadUpperImmediate(Register::Rg0, 0).opcode(),
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0xC
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);
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}
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#[test]
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fn test_opcode_jump_instructions() {
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assert_eq!(Instruction::Jump(Register::Rg0, 0).opcode(), 0xD);
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assert_eq!(Instruction::JumpEq(Register::Rg0, 0).opcode(), 0xE);
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assert_eq!(Instruction::JumpNeq(Register::Rg0, 0).opcode(), 0xF);
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assert_eq!(Instruction::JumpGt(Register::Rg0, 0).opcode(), 0x10);
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assert_eq!(Instruction::JumpGe(Register::Rg0, 0).opcode(), 0x11);
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assert_eq!(Instruction::JumpLt(Register::Rg0, 0).opcode(), 0x12);
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assert_eq!(Instruction::JumpLe(Register::Rg0, 0).opcode(), 0x13);
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}
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#[test]
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fn test_opcode_arithmetic_instructions() {
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assert_eq!(
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Instruction::Compare(Register::Rg0, Register::Rg1).opcode(),
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0x14
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);
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assert_eq!(Instruction::Increment(Register::Rg0).opcode(), 0x15);
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assert_eq!(Instruction::Decrement(Register::Rg0).opcode(), 0x16);
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assert_eq!(
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Instruction::ShiftLeft(Register::Rg0, Register::Rg1, 0).opcode(),
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0x17
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);
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assert_eq!(
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Instruction::ShiftRight(Register::Rg0, Register::Rg1, 0).opcode(),
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0x18
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);
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assert_eq!(
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Instruction::Add(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x19
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);
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assert_eq!(
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Instruction::Sub(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x1A
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);
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}
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#[test]
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fn test_opcode_logical_instructions() {
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assert_eq!(
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Instruction::And(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x1B
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);
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assert_eq!(
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Instruction::Or(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x1C
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);
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assert_eq!(
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Instruction::Not(Register::Rg0, Register::Rg1).opcode(),
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0x1D
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);
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assert_eq!(
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Instruction::Xor(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x1E
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);
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assert_eq!(
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Instruction::Nand(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x1F
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);
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assert_eq!(
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Instruction::Nor(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x20
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);
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assert_eq!(
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Instruction::Xnor(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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0x21
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);
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}
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#[test]
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fn test_opcode_system_instructions() {
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assert_eq!(
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Instruction::Interrupt(Interrupt::Software(0)).opcode(),
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0x22
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);
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assert_eq!(Instruction::IntReturn.opcode(), 0x23);
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}
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#[test]
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fn test_opcode_top_bits_are_zero() {
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// Test that opcodes have top 2 bits as 0 (6-bit opcodes)
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let instructions = [
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Instruction::Nop,
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Instruction::Mov(Register::Rg0, Register::Rg1),
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Instruction::Add(Register::Rg0, Register::Rg1, Register::Rg2),
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Instruction::Halt,
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];
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for instruction in instructions {
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let opcode = instruction.opcode();
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assert_eq!(
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opcode & 0xC0,
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0,
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"Top 2 bits should be 0 for opcode {opcode:#02x}"
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);
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}
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}
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#[test]
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fn test_opcode_same_instruction_different_params() {
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// Same instruction type with different parameters should have same opcode
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assert_eq!(
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Instruction::Mov(Register::Rg0, Register::Rg1).opcode(),
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Instruction::Mov(Register::Acc, Register::Spr).opcode()
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);
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assert_eq!(
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Instruction::Add(Register::Rg0, Register::Rg1, Register::Rg2).opcode(),
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Instruction::Add(Register::Acc, Register::Spr, Register::Bpr).opcode()
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);
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assert_eq!(
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Instruction::LoadWord(Register::Rg0, 100, Register::Rg1).opcode(),
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Instruction::LoadWord(Register::Acc, 500, Register::Spr).opcode()
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);
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}
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@@ -48,7 +48,7 @@ impl Processor {
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// decode and execute the instruction
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let instruction = Instruction::decode(val);
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instruction.clone().execute(self);
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instruction.execute(self);
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instruction
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}
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