zxq5/damn_simple_architecture
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merge zxq5 changes with mine lol

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This commit is contained in:
J. Hinchliffe
2025-06-19 15:53:55 +01:00
parent 81433dcbcd d5a690563b
commit 7bdeab58a1
3 changed files with 10 additions and 37 deletions
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common/src/instructions/encode/tests.rs
+9 -6
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@@ -5,7 +5,7 @@ fn test_encode_nop() {
let no_reg = Register::NoReg as u32;
let no_op = u32::from(Instruction::Nop.opcode());
let expected = no_op << 26 | no_reg << 21 | no_reg << 16 | no_reg << 11;
let expected = (no_op << 26) | (no_reg << 21) | (no_reg << 16) | (no_reg << 11);
let got = Instruction::Nop.encode();
assert_eq!(expected, got);
@@ -25,7 +25,7 @@ fn test_encode_mov() {
));
let mov = u32::from(instruction.opcode());
let expected = mov << 26 | rg0 << 21 | no_reg << 16 | rg1 << 11;
let expected = (mov << 26) | (rg0 << 21) | (no_reg << 16) | (rg1 << 11);
let got = instruction.encode();
assert_eq!(expected, got);
@@ -44,7 +44,7 @@ fn test_encode_load_byte() {
));
let load_byte = u32::from(instruction.opcode());
let expected = load_byte << 26 | rg0 << 21 | rg1 << 16 | u32::from(immediate);
let expected = (load_byte << 26) | (rg0 << 21) | (rg1 << 16) | u32::from(immediate);
let got = instruction.encode();
assert_eq!(expected, got);
@@ -65,8 +65,11 @@ fn test_encode_shift_left_shamt() {
));
let shift_left = u32::from(instruction.opcode());
let expected =
shift_left << 26 | rg0 << 21 | no_reg << 16 | no_reg << 11 | u32::from(shift_amount) << 6;
let expected = (shift_left << 26)
| (rg0 << 21)
| (no_reg << 16)
| (no_reg << 11)
| (u32::from(shift_amount) << 6);
let got = instruction.encode();
@@ -87,7 +90,7 @@ fn test_encode_shift_left_reg() {
));
let shift_left = u32::from(instruction.opcode());
let expected = shift_left << 26 | rg0 << 21 | rg1 << 16 | no_reg << 11;
let expected = (shift_left << 26) | (rg0 << 21) | (rg1 << 16) | (no_reg << 11);
let got = instruction.encode();