merge zxq5 changes with mine lol

.vscode/settings.json

@@ -2,4 +2,4 @@
   "rust-analyzer.check.command": "clippy",
   "editor.formatOnSave": true,
   "rust-analyzer.cargo.features": "all"
-}
+}

assembler/src/parser.rs

@@ -305,34 +305,4 @@ impl Parser {
             Ok(self.tokens.last().unwrap().clone())
         }
     }
-
-    fn expect(&mut self, type_: TokenType) -> Result<Token, AssembleError> {
-        let tok = self.next()?;
-
-        if TokenType::from_token(&tok) == type_ {
-            Ok(tok)
-        } else {
-            Err(AssembleError::UnexpectedToken(tok, type_))
-        }
-    }
-
-    fn expect_any(&mut self, types: &[TokenType]) -> Result<Token, AssembleError> {
-        let tok = self.next()?;
-
-        if types.contains(&TokenType::from_token(&tok)) {
-            Ok(tok)
-        } else {
-            Err(AssembleError::UnexpectedToken(tok, types[0]))
-        }
-    }
-
-    fn maybe_expect(&mut self, types: &[TokenType]) -> Option<Token> {
-        let tok = self.peek_next().ok()?;
-
-        if types.contains(&TokenType::from_token(&tok)) {
-            Some(tok.clone())
-        } else {
-            None
-        }
-    }
 }

common/src/instructions/encode/tests.rs

@@ -5,7 +5,7 @@ fn test_encode_nop() {
     let no_reg = Register::NoReg as u32;
     let no_op = u32::from(Instruction::Nop.opcode());
 
-    let expected = no_op << 26 | no_reg << 21 | no_reg << 16 | no_reg << 11;
+    let expected = (no_op << 26) | (no_reg << 21) | (no_reg << 16) | (no_reg << 11);
     let got = Instruction::Nop.encode();
 
     assert_eq!(expected, got);
@@ -25,7 +25,7 @@ fn test_encode_mov() {
     ));
     let mov = u32::from(instruction.opcode());
 
-    let expected = mov << 26 | rg0 << 21 | no_reg << 16 | rg1 << 11;
+    let expected = (mov << 26) | (rg0 << 21) | (no_reg << 16) | (rg1 << 11);
     let got = instruction.encode();
 
     assert_eq!(expected, got);
@@ -44,7 +44,7 @@ fn test_encode_load_byte() {
     ));
     let load_byte = u32::from(instruction.opcode());
 
-    let expected = load_byte << 26 | rg0 << 21 | rg1 << 16 | u32::from(immediate);
+    let expected = (load_byte << 26) | (rg0 << 21) | (rg1 << 16) | u32::from(immediate);
     let got = instruction.encode();
 
     assert_eq!(expected, got);
@@ -65,8 +65,11 @@ fn test_encode_shift_left_shamt() {
     ));
     let shift_left = u32::from(instruction.opcode());
 
-    let expected =
-        shift_left << 26 | rg0 << 21 | no_reg << 16 | no_reg << 11 | u32::from(shift_amount) << 6;
+    let expected = (shift_left << 26)
+        | (rg0 << 21)
+        | (no_reg << 16)
+        | (no_reg << 11)
+        | (u32::from(shift_amount) << 6);
 
     let got = instruction.encode();
 
@@ -87,7 +90,7 @@ fn test_encode_shift_left_reg() {
     ));
     let shift_left = u32::from(instruction.opcode());
 
-    let expected = shift_left << 26 | rg0 << 21 | rg1 << 16 | no_reg << 11;
+    let expected = (shift_left << 26) | (rg0 << 21) | (rg1 << 16) | (no_reg << 11);
 
     let got = instruction.encode();