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tests: update to reflect new argument ordering

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This commit is contained in:
J. Hinchliffe
2025-06-19 16:46:07 +01:00
parent 6f834025ed
commit 78512d95e9
2 changed files with 54 additions and 22 deletions
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common/src/instructions/tests.rs
+6 -2
View File
@@ -196,8 +196,12 @@ fn test_instruction_decode_misc() {
#[test]
fn test_instruction_decode_invalid() {
// Test with invalid opcode.
let invalid_encoded = 0xFF00_0000;
assert!(Instruction::decode(invalid_encoded).is_err());
let invalid_encoded = 0xF500_0000;
let decode = Instruction::decode(invalid_encoded);
dbg!(&decode);
assert!(decode.is_err());
}
// TODO: Get interrupts working.
emulator/src/emulator/system/processor/tests.rs
+48 -20
View File
@@ -64,8 +64,11 @@ fn test_load_byte_instruction() {
cpu.memory.write_byte(addr, 0xAB);
*cpu.reg(Register::Rg1) = addr - 4;
let load_byte_instr =
Instruction::LoadByte(ITypeArgs::new(4, Some(Register::Rg1), Some(Register::Rg2)));
let load_byte_instr = Instruction::LoadByte(ITypeArgs::new(
4,
Some(Register::Rg1),
Some(Register::Rg2),
));
load_byte_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg2), 0x0000_00AB);
@@ -78,8 +81,11 @@ fn test_load_byte_signed_instruction() {
cpu.memory.write_byte(addr, 0xFF);
*cpu.reg(Register::Rg1) = addr;
let load_byte_signed_instr =
Instruction::LoadByteSigned(ITypeArgs::new(0, Some(Register::Rg1), Some(Register::Rg2)));
let load_byte_signed_instr = Instruction::LoadByteSigned(ITypeArgs::new(
0,
Some(Register::Rg1),
Some(Register::Rg2),
));
load_byte_signed_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg2), 0xFFFF_FFFF);
@@ -92,8 +98,11 @@ fn test_load_halfword_instruction() {
cpu.memory.write_word(addr, 0x1234_5678);
*cpu.reg(Register::Rg1) = addr;
let load_halfword_instr =
Instruction::LoadHalfword(ITypeArgs::new(0, Some(Register::Rg1), Some(Register::Rg2)));
let load_halfword_instr = Instruction::LoadHalfword(ITypeArgs::new(
0,
Some(Register::Rg1),
Some(Register::Rg2),
));
load_halfword_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg2), 0x0000_1234);
@@ -106,8 +115,11 @@ fn test_load_word_instruction() {
cpu.memory.write_word(addr, 0x1234_5678);
*cpu.reg(Register::Rg1) = addr;
let load_word_instr =
Instruction::LoadWord(ITypeArgs::new(0, Some(Register::Rg1), Some(Register::Rg2)));
let load_word_instr = Instruction::LoadWord(ITypeArgs::new(
0,
Some(Register::Rg1),
Some(Register::Rg2),
));
load_word_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg2), 0x1234_5678);
@@ -120,8 +132,11 @@ fn test_store_byte_instruction() {
*cpu.reg(Register::Rg1) = addr;
*cpu.reg(Register::Rg2) = 0xAB;
let store_byte_instr =
Instruction::StoreByte(ITypeArgs::new(0, Some(Register::Rg1), Some(Register::Rg2)));
let store_byte_instr = Instruction::StoreByte(ITypeArgs::new(
0,
Some(Register::Rg2),
Some(Register::Rg1),
));
store_byte_instr.execute(&mut cpu);
assert_eq!(cpu.memory.read_byte(addr), 0xAB);
@@ -134,8 +149,11 @@ fn test_store_word_instruction() {
*cpu.reg(Register::Rg1) = addr;
*cpu.reg(Register::Rg2) = 0x1234_5678;
let store_word_instr =
Instruction::StoreWord(ITypeArgs::new(0, Some(Register::Rg1), Some(Register::Rg2)));
let store_word_instr = Instruction::StoreWord(ITypeArgs::new(
0,
Some(Register::Rg2),
Some(Register::Rg1),
));
store_word_instr.execute(&mut cpu);
assert_eq!(cpu.memory.read_word(addr), 0x1234_5678);
@@ -307,7 +325,8 @@ fn test_increment_instruction() {
let mut cpu = create_test_processor();
*cpu.reg(Register::Rg1) = 42;
let inc_instr = Instruction::Increment(RTypeArgs::new(Some(Register::Rg1), None, None, None));
let inc_instr =
Instruction::Increment(RTypeArgs::new(Some(Register::Rg1), None, None, None));
inc_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg1), 43);
@@ -318,7 +337,8 @@ fn test_decrement_instruction() {
let mut cpu = create_test_processor();
*cpu.reg(Register::Rg1) = 42;
let dec_instr = Instruction::Decrement(RTypeArgs::new(Some(Register::Rg1), None, None, None));
let dec_instr =
Instruction::Decrement(RTypeArgs::new(Some(Register::Rg1), None, None, None));
dec_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg1), 41);
@@ -377,8 +397,11 @@ fn test_shift_left_with_register() {
fn test_load_lower_immediate() {
let mut cpu = create_test_processor();
let lli_instr =
Instruction::LoadLowerImmediate(ITypeArgs::new(0x1234, Some(Register::Rg1), None));
let lli_instr = Instruction::LoadLowerImmediate(ITypeArgs::new(
0x1234,
Some(Register::Rg1),
None,
));
lli_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg1), 0x0000_1234);
@@ -389,8 +412,11 @@ fn test_load_upper_immediate() {
let mut cpu = create_test_processor();
*cpu.reg(Register::Rg1) = 0x0000_5678;
let lui_instr =
Instruction::LoadUpperImmediate(ITypeArgs::new(0x1234, Some(Register::Rg1), None));
let lui_instr = Instruction::LoadUpperImmediate(ITypeArgs::new(
0x1234,
Some(Register::Rg1),
None,
));
lui_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Rg1), 0x1234_5678);
@@ -415,7 +441,8 @@ fn test_jump_equal_when_flag_set() {
cpu.set_flag(Flag::Equal, true);
*cpu.reg(Register::Rg1) = 0x1000;
let jump_eq_instr = Instruction::JumpEq(ITypeArgs::new(0x100, Some(Register::Rg1), None));
let jump_eq_instr =
Instruction::JumpEq(ITypeArgs::new(0x100, Some(Register::Rg1), None));
jump_eq_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Pcx), 0x1100);
@@ -428,7 +455,8 @@ fn test_jump_equal_when_flag_not_set() {
*cpu.reg(Register::Rg1) = 0x1000;
let initial_pc = cpu.get(Register::Pcx);
let jump_eq_instr = Instruction::JumpEq(ITypeArgs::new(0x100, Some(Register::Rg1), None));
let jump_eq_instr =
Instruction::JumpEq(ITypeArgs::new(0x100, Some(Register::Rg1), None));
jump_eq_instr.execute(&mut cpu);
assert_eq!(cpu.get(Register::Pcx), initial_pc);