written up instruction set

.gitignore

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+/target

Cargo.lock

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+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 4
+
+[[package]]
+name = "damn_simple_architecture"
+version = "0.1.0"

Cargo.toml

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+[package]
+name = "damn_simple_architecture"
+version = "0.1.0"
+edition = "2024"
+
+[lib]
+name = "dsa_rs"
+path = "src/lib.rs"
+
+[dependencies]

README.md

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+We failing DSA with this one

src/common/instructions.rs

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+pub enum Instruction {
+    // No-op
+    Nop,
+    
+    // Data transfer instructions
+    Mov(Register, Register),
+    MovSigned(Register, Register),
+
+    LoadByte(Register, Offset, Register),
+    LoadByteSigned(Register, Offset, Register),
+    LoadHalfword(Register, Offset, Register),
+    LoadHalfwordSigned(Register, Offset, Register),
+    LoadWord(Register, Offset, Register),
+    LoadWordSigned(Register, Offset, Register),
+
+    StoreByte(Register, Offset, Register),
+    StoreHalfword(Register, Offset, Register),
+    StoreWord(Register, Offset, Register),
+
+    LoadLowerImmediate(Register, Immediate),
+    LoadUpperImmediate(Register, Immediate),
+
+    // Jump Instructions
+    Jump(Register, Offset),
+    JumpEq(Register, Offset),
+    JumpNeq(Register, Offset),
+    JumpGt(Register, Offset),
+    JumpGe(Register, Offset),
+    JumpLt(Register, Offset),
+    JumpLe(Register, Offset),
+
+    // Comparison
+    Compare(Register, Register),
+
+    // Arithmetic
+    Add(Register, Register, Register),
+    Sub(Register, Register, Register),
+    Increment(Register),
+    Decrement(Register),
+    ShiftLeft(Register, Register, Register),
+    ShiftRight(Register, Register, Register),
+
+    // Logical
+    And(Register, Register, Register),
+    Or(Register, Register, Register),
+    Not(Register, Register),
+    Xor(Register, Register, Register),
+    Nand(Register, Register, Register),
+    Nor(Register, Register, Register),
+    Xnor(Register, Register, Register),
+
+    // Misc
+    Interrupt(Interrupt),
+    IntReturn,
+    Halt,
+}
+
+type Offset = u16;
+type Immediate = u16;
+
+pub enum Interrupt {
+    Software(u8)
+}
+
+impl Into<u8> for Interrupt {
+    fn into(self) -> u8 {
+        match self {
+            Interrupt::Software(code) => code,
+        }
+    }
+}
+
+impl From<u8> for Interrupt {
+    fn from(code: u8) -> Self {
+        todo!("implement this once a hardware interrupt convention is established");
+        Interrupt::Software(code)
+    }
+}
+
+pub enum Register {
+    // general purpose registers
+    Rg0,
+    Rg1,
+    Rg2,
+    Rg3,
+    Rg4,
+    Rg5,
+    Rg6,
+    Rg7,
+    Rg8,
+    Rg9,
+    Rg10,
+    Rg11,
+    Rg12,
+    Rg13,
+    Rg14,
+    Rg15,
+
+    // special purpose registers
+    Acc,
+    Spr,
+    Bpr,
+    Ret,
+    Idr,
+    Mmr,
+    Zero,
+    None,
+
+    // system registers - can't be written to by instructions.
+    Mar,
+    Mdr,
+    Sts,
+    Cir,
+    Pcx,
+}

src/common/mod.rs

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+pub mod instructions;

src/lib.rs

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+pub mod common;

src/main.rs

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+
+
+fn main() {
+    println!("Hello, world!");
+}