From 68c8da42713304525da16e2ed2ad7fae66813a29 Mon Sep 17 00:00:00 2001
From: zxq5 <zxq5@zxq5.dev>
Date: Sat, 14 Jun 2025 03:09:30 +0100
Subject: [PATCH] written up instruction set

---
 .gitignore                 |   1 +
 Cargo.lock                 |   7 +++
 Cargo.toml                 |  10 ++++
 README.md                  |   1 +
 src/common/instructions.rs | 115 +++++++++++++++++++++++++++++++++++++
 src/common/mod.rs          |   1 +
 src/lib.rs                 |   1 +
 src/main.rs                |   5 ++
 8 files changed, 141 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 Cargo.lock
 create mode 100644 Cargo.toml
 create mode 100644 README.md
 create mode 100644 src/common/instructions.rs
 create mode 100644 src/common/mod.rs
 create mode 100644 src/lib.rs
 create mode 100644 src/main.rs

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ea8c4bf
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+/target
diff --git a/Cargo.lock b/Cargo.lock
new file mode 100644
index 0000000..b14b0b3
--- /dev/null
+++ b/Cargo.lock
@@ -0,0 +1,7 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 4
+
+[[package]]
+name = "damn_simple_architecture"
+version = "0.1.0"
diff --git a/Cargo.toml b/Cargo.toml
new file mode 100644
index 0000000..d8c29d0
--- /dev/null
+++ b/Cargo.toml
@@ -0,0 +1,10 @@
+[package]
+name = "damn_simple_architecture"
+version = "0.1.0"
+edition = "2024"
+
+[lib]
+name = "dsa_rs"
+path = "src/lib.rs"
+
+[dependencies]
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..98498f8
--- /dev/null
+++ b/README.md
@@ -0,0 +1 @@
+We failing DSA with this one
\ No newline at end of file
diff --git a/src/common/instructions.rs b/src/common/instructions.rs
new file mode 100644
index 0000000..1253999
--- /dev/null
+++ b/src/common/instructions.rs
@@ -0,0 +1,115 @@
+pub enum Instruction {
+    // No-op
+    Nop,
+    
+    // Data transfer instructions
+    Mov(Register, Register),
+    MovSigned(Register, Register),
+
+    LoadByte(Register, Offset, Register),
+    LoadByteSigned(Register, Offset, Register),
+    LoadHalfword(Register, Offset, Register),
+    LoadHalfwordSigned(Register, Offset, Register),
+    LoadWord(Register, Offset, Register),
+    LoadWordSigned(Register, Offset, Register),
+
+    StoreByte(Register, Offset, Register),
+    StoreHalfword(Register, Offset, Register),
+    StoreWord(Register, Offset, Register),
+
+    LoadLowerImmediate(Register, Immediate),
+    LoadUpperImmediate(Register, Immediate),
+
+    // Jump Instructions
+    Jump(Register, Offset),
+    JumpEq(Register, Offset),
+    JumpNeq(Register, Offset),
+    JumpGt(Register, Offset),
+    JumpGe(Register, Offset),
+    JumpLt(Register, Offset),
+    JumpLe(Register, Offset),
+
+    // Comparison
+    Compare(Register, Register),
+
+    // Arithmetic
+    Add(Register, Register, Register),
+    Sub(Register, Register, Register),
+    Increment(Register),
+    Decrement(Register),
+    ShiftLeft(Register, Register, Register),
+    ShiftRight(Register, Register, Register),
+
+    // Logical
+    And(Register, Register, Register),
+    Or(Register, Register, Register),
+    Not(Register, Register),
+    Xor(Register, Register, Register),
+    Nand(Register, Register, Register),
+    Nor(Register, Register, Register),
+    Xnor(Register, Register, Register),
+
+    // Misc
+    Interrupt(Interrupt),
+    IntReturn,
+    Halt,
+}
+
+type Offset = u16;
+type Immediate = u16;
+
+pub enum Interrupt {
+    Software(u8)
+}
+
+impl Into<u8> for Interrupt {
+    fn into(self) -> u8 {
+        match self {
+            Interrupt::Software(code) => code,
+        }
+    }
+}
+
+impl From<u8> for Interrupt {
+    fn from(code: u8) -> Self {
+        todo!("implement this once a hardware interrupt convention is established");
+        Interrupt::Software(code)
+    }
+}
+
+pub enum Register {
+    // general purpose registers
+    Rg0,
+    Rg1,
+    Rg2,
+    Rg3,
+    Rg4,
+    Rg5,
+    Rg6,
+    Rg7,
+    Rg8,
+    Rg9,
+    Rg10,
+    Rg11,
+    Rg12,
+    Rg13,
+    Rg14,
+    Rg15,
+
+    // special purpose registers
+    Acc,
+    Spr,
+    Bpr,
+    Ret,
+    Idr,
+    Mmr,
+    Zero,
+    None,
+
+    // system registers - can't be written to by instructions.
+    Mar,
+    Mdr,
+    Sts,
+    Cir,
+    Pcx,
+}
\ No newline at end of file
diff --git a/src/common/mod.rs b/src/common/mod.rs
new file mode 100644
index 0000000..2a9d2e5
--- /dev/null
+++ b/src/common/mod.rs
@@ -0,0 +1 @@
+pub mod instructions;
\ No newline at end of file
diff --git a/src/lib.rs b/src/lib.rs
new file mode 100644
index 0000000..ffac467
--- /dev/null
+++ b/src/lib.rs
@@ -0,0 +1 @@
+pub mod common;
\ No newline at end of file
diff --git a/src/main.rs b/src/main.rs
new file mode 100644
index 0000000..ed1ffda
--- /dev/null
+++ b/src/main.rs
@@ -0,0 +1,5 @@
+
+
+fn main() {
+    println!("Hello, world!");
+}