147 lines
3.8 KiB
Markdown
147 lines
3.8 KiB
Markdown
## Architecture
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32 bit instruction width/word size
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## Instruction Types:
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Type Sizes:
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- u16: [16 bits]
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- u6: [6 bits]
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- Reg: [5 bits]
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- Opcode: [6 bits]
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Instruction Types:
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- R: [Opcode] [Reg] [Reg] [Reg] [Reg] [u6]
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- I: [Opcode] [Reg] [Reg] [u16 ]
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## Instruction Set
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// move
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mov <src: Reg> <dst: Reg> [ unused ]
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cmov <src: Reg> <dst: Reg> <cmp: Reg>
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// load
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ldb <src: Reg> <dst: Reg> <offset: u16>
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ldbs <src: Reg> <dst: Reg> <offset: u16>
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ldh <src: Reg> <dst: Reg> <offset: u16>
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ldhs <src: Reg> <dst: Reg> <offset: u16>
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ldw <src: Reg> <dst: Reg> <offset: u16>
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// store
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stb <src: Reg> <dst: Reg> <offset: u16>
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sth <src: Reg> <dst: Reg> <offset: u16>
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stw <src: Reg> <dst: Reg> <offset: u16>
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// immediate
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lli <dst: Reg> [unused] <imm: u16>
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lui <dst: Reg> [unused] <imm: u16>
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// comparison
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ieq <sr1: Reg> <sr2: Reg> <dst: Reg> [unused]
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ine <sr1: Reg> <sr2: Reg> <dst: Reg> [unused]
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igt <sr1: Reg> <sr2: Reg> <dst: Reg> [unused]
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ige <sr1: Reg> <sr2: Reg> <dst: Reg> [unused]
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ilt <sr1: Reg> <sr2: Reg> <dst: Reg> [unused]
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ile <sr1: Reg> <sr2: Reg> <dst: Reg> [unused]
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// Jump
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jmp [ unused ] <addr: Reg> <offset: u16> // unconditional
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jez <cmp: Reg> <addr: Reg> <offset: u16> // conditional on cmp == 0
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jnz <cmp: Reg> <addr: Reg> <offset: u16>
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jic [ unused ] <addr: Reg> <offset: u16> // conditional on carry
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jnc [ unused ] <addr: Reg> <offset: u16>
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// Bitwise
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and <sr1: Reg> <sr2: Reg> <dst: Reg> [unused] // and
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nnd <sr1: Reg> <sr2: Reg> <dst: Reg> [unused] // nand
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or <sr1: Reg> <sr2: Reg> <dst: Reg> [unused] // or
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nor <sr1: Reg> <sr2: Reg> <dst: Reg> [unused] // nor
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xor <sr1: Reg> <sr2: Reg> <dst: Reg> [unused] // xor
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xnr <sr1: Reg> <sr2: Reg> <dst: Reg> [unused] // xnor
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not <src: Reg> [ unused ] <dst: Reg> [unused] // not
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// Arithmetic
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add <sr1: Reg> <sr2: Reg> <dst: Reg>
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sub <sr1: Reg> <sr2: Reg> <dst: Reg>
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shl <src: Reg> <rshamt: Reg> <dst: Reg> <ishamt: u6> // left shift of rshamt+ishamt
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shr <src: Reg> <rshamt: Reg> <dst: Reg> <ishamt: u6> // right shift
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// Immediate Arithmetic
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addi <sr1: Reg> <dst: Reg> <imm: u16>
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subi <sr1: Reg> <dst: Reg> <imm: u16>
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// Misc
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nop (zero/do nothing)
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int <imm: u6>
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hlt
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// Atomic
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// Atomic Compare and Swap - compares src and dst, if src
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acs <src: Reg> <cmp: Reg> <dst: Reg> <res: Reg>
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## Assembler Pseudoinstructions
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Definitions:
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Label - named address, a function or global
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```
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lwi <src: Label|Imm> <dest: Reg> // loads the literal value of Label|Imm into dest
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// if src is a Label, take literal value of Label
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=> lli $src, $dest
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=> lui $src, $dest
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lli <src: Label> <dest: Reg> // loads the lower 16 bits of the literal value of Label into dest
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... -> similarly defined for lui
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ldw <src: Label> <dest: Reg> // loads the word at the address of Label into dest
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... => similarly defined for ldb, ldbs, ldh, ldhs
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// load the label value of src into dest with lui/lli
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=> lli $src, $dest
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=> lui $src, $dest
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=> ldw $dest, $dest
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stw <src: Reg> <dest: Label> // stores the word in src using the address/label that is dest.
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// load the literal value of dest into the accumulator with lui/lli
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=> lli $dest, acc
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=> lui $dest, acc
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=> stw $src, acc
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jmp <dest: Label>
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CASE dest > u16::MAX:
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=> lli $dest, acc
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=> lui $dest, acc
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=> jmp $dest, 0
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CASE dest < u16::MAX:
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// assembler inserts the literal value of dest
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=> jmp $dest, 0
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jmp <lbl: Label> <dest: Reg>
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CASE lbl > u16::MAX:
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AssemblerError!
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CASE lbl < u16::MAX:
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=> jmp $dest, lbl
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call <addr: Label>
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=> subi spr, 4, spr
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=> stw pcx, spr, 0
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=> jmp $addr
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func
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// push bpr
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=> subi spr, 4, spr
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=> stw bpr, spr, 0
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// replace bpr with spr
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=> mov spr, bpr
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return
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=> mov bpr, spr
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// pop bpr
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=> addi spr, 4, spr
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=> ldw spr, bpr, 0
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// load return addr
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=> ldw spr, ret, 0
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=> addi, spr, 4, spr
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=> jmp ret, 4
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```
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