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Update Instruction Set

zxq5
2025-06-16 16:16:49 +01:00
parent 5042140051
commit f398a28240
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Instruction-Set.md
+43 -53
@@ -51,57 +51,47 @@ The jump range: 256MB region around current PC. For longer jumps than this, see
To compute this address, the linker should find the address of the label, cut off the top 4 bits, then rightward shift twice. The CPU will then convert this to the actual 32-bit address following the steps outlined above.
### Load/Store and Data Movement Instructions
| Hex | Code | Operands | Description |
|--------|------|--------------------|--------------------------------------------------------------------------------------------------|
| 0x01 | MOV | [reg0, reg1] | Copies the value from reg0 to reg1. |
| 0x02 | LDB | [reg, offset(base)]| Loads a byte from memory address (base + offset) into `reg'. The effective address must be byte-aligned.|
| 0x03 | LDH | [reg, offset(base)]| Loads a half-word (2 bytes) from memory address (base + offset) into `reg'. The effective address must be 2-byte aligned.|
| 0x04 | LDW | [reg, offset(base)]| Loads a word (4 bytes) from memory address (base + offset) into `reg'. The effective address must be 4-byte aligned.|
| 0x05 | STB | [reg, offset(base)]| Stores the least significant byte in `reg' into memory at address (base + offset). The effective address must be byte-aligned.|
| 0x06 | STH | [reg, offset(base)]| Stores a half-word (the least significant 16 bits) from `reg' into memory at address (base + offset). The effective address must be 2-byte aligned.|
| 0x07 | STW | [reg, offset(base)]| Stores a word (4 bytes) from `reg' into memory at address (base + offset). The effective address must be 4-byte aligned.|
| 0x21 | PSH | [reg] | Pushes the value in the specified register onto the stack. |
| 0x22 | POP | [reg] | Pops the value from the stack into the specified register. |
| 0x23 | LUI | [value, reg] | Loads a 16-bit sign-extended literal value into reg, setting the top 16 bits of the word. To populate the lower 16 bits, see LLI.|
| 0x24 | LLI | [value, reg] | Loads a 16-bit sign-extended literal value into reg, setting the bottom 16 bits of the word. To populate the upper 16 bits, see LLI.|
### Instructions
# Processor Instruction Set Reference
### Arithmetic Instructions
| Hex | Code | Operands | Description |
|--------|------|----------|-------------------------------------------------------------------------|
| 0x08 | ADD | [reg] | Adds the value in the specified register to the value in the accumulator.|
| 0x09 | SUB | [reg] | Subtracts the value in the specified register from the value in the accumulator.|
| 0x0A | INC | [reg] | Increments the value in the given register. |
| 0x0B | DEC | [reg] | Decrements the value in the given register. |
### Logical Instructions
| Hex | Code | Operands | Description |
|--------|------|-------------------|---------------------------------------------------|
| 0x0E | AND | [reg1, reg2, dest]| Performs bitwise AND function on two values. |
| 0x0F | ORR | [reg1, reg2, dest]| Performs bitwise OR function on two values. |
| 0x10 | NOT | [reg1, dest] | Performs bitwise NOT function on a value. |
| 0x11 | XOR | [reg1, reg2, dest]| Performs bitwise XOR function on two values. |
| 0x12 | NAND | [reg1, reg2, dest]| Performs bitwise NAND function on two values. |
| 0x13 | NOR | [reg1, reg2, dest]| Performs bitwise NOR function on two values. |
| 0x14 | XNOR | [reg1, reg2, dest]| Performs logical XNOR function on two values. |
### Shift Instructions
| Hex | Code | Operands | Description |
|--------|------|----------|---------------------------------------------------------|
| 0x0C | SHL | [reg] | Shifts the value in the specified register left by one bit.|
| 0x0D | SHR | [reg] | Shifts the value in the specified register right by one bit.|
### Control Flow Instructions
| Hex | Code | Operands | Description |
|--------|------|----------|---------------------------------------------------------------------------|
| 0x16 | JMP | [addr] | Unconditionally jumps to addr. |
| 0x17 | JEQ | [addr] | Jumps to addr if equal flag set. |
| 0x18 | JNE | [addr] | Jumps to addr if equal flag not set. |
| 0x19 | JGT | [addr] | Jumps to addr if greater than flag set. |
| 0x1A | JGE | [addr] | Jumps to addr if greater than flag or equal flag set. |
| 0x1B | JLT | [addr] | Jumps to addr if less than flag set. |
| 0x1C | JLE | [addr] | Jumps to addr if less than flag or equal flag set. |
| 0x1F | CLL | [addr] | Performs a jump, saving the return address to the RET register. |
| 0x20 | RET | n/a | Returns from a subroutine using the address in the RET register. |
| 0x1E | INT | [int code]| Initiates an interrupt with the given interrupt code. |
| 0x25 | IRT | n/a | IRET instruction to return from interrupts. |
| Hex | Mnemonic | Operands | Description | Type |
|------|----------|----------|-------------|------|
| 0x00 | NOP | n/a | No operation - a blank line. | |
| 0x01 | MOV | SrcReg, DestReg | Copies from SrcReg to DestReg. | |
| 0x02 | MOVS | SrcReg, DestReg | Copies from SrcReg to DestReg, sign extending the value to take up a full word. | |
| 0x03 | LDB | BaseReg, Offset, DestReg | Loads a byte from memory address (base + offset) into DestReg. The effective address must be byte-aligned. | |
| 0x04 | LDBS | BaseReg, Offset, DestReg | Loads a sign-extended byte from memory address (base + offset) into DestReg. The effective address must be byte-aligned. | |
| 0x05 | LDH | BaseReg, Offset, DestReg | Loads a half-word from memory address (base + offset) into DestReg. The effective address must be 2-byte-aligned. | |
| 0x06 | LDHS | BaseReg, Offset, DestReg | Loads a sign-extended half-word from memory address (base + offset) into DestReg. The effective address must be 2-byte-aligned. | |
| 0x07 | LDW | BaseReg, Offset, DestReg | Loads a word from memory address (base + offset) into DestReg. The effective address must be 4-byte-aligned. | |
| 0x08 | STB | SrcReg, BaseReg, Offset | Stores a byte from SrcReg in memory address (base + offset). The effective address must be byte-aligned. | |
| 0x09 | STH | SrcReg, BaseReg, Offset | Stores a half-word from SrcReg in memory address (base + offset). The effective address must be 2-byte-aligned. | |
| 0x0A | STW | SrcReg, BaseReg, Offset | Stores a word from SrcReg in memory address (base + offset). The effective address must be 4-byte-aligned. | |
| 0x0B | LLI | DstReg, Value | Loads a 16-bit literal value into reg, setting the bottom 16 bits of the word. To populate the upper 16 bits, see LUI. | |
| 0x0C | LUI | DstReg, Value | Loads a 16-bit literal value into reg, setting the top 16 bits of the word. To populate the lower 16 bits, see LLI. | |
| 0x0D | JMP | DestReg, Offset \| Address | Unconditionally jumps to the calculated address or direct address. | |
| 0x0E | JEQ | DestReg, Offset \| Address | Jumps to the calculated address or direct address if equal flag set. | |
| 0x0F | JNE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if the equal flag is not set. | |
| 0x10 | JGT | DestReg, Offset \| Address | Jumps to the calculated address or direct address if greater than flag set. | |
| 0x11 | JGE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if greater than flag or equal flag set. | |
| 0x12 | JLT | DestReg, Offset \| Address | Jumps to the calculated address or direct address if less than flag set. | |
| 0x13 | JLE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if less than flag or equal flag set. | |
| 0x14 | CMP | Reg1, Reg2 | Compares the value of Reg1 to the value in Reg2. The results of the comparisons are set in the Status register. | |
| 0x15 | INC | Reg | Increments the value in the given register. | |
| 0x16 | DEC | Reg | Decrements the value in the given register. | |
| 0x17 | SHL | Reg, Literal \| ValReg | Left shifts the value in Reg by the given amount (either a register, or a literal value). | |
| 0x18 | SHR | Reg, Literal \| ValReg | Right shifts the value in Reg by the given amount (either a register, or a literal value). | |
| 0x19 | ADD | Src1, Src2, Dest | Adds the value of Src2 to Src1 and writes the result to Dest. | |
| 0x1A | SUB | Src1, Src2, Dest | Subtracts the value of Src2 from Src1 and writes the result to Dest. | |
| 0x1B | AND | Src1, Src2, Dest | Performs bitwise AND on Src1 and Src2 storing the result in Dest. | |
| 0x1C | OR | Src1, Src2, Dest | Performs bitwise OR on Src1 and Src2 storing the result in Dest. | |
| 0x1D | NOT | Src, Dest | Performs bitwise NOT on Src storing the result in Dest. | |
| 0x1E | XOR | Src1, Src2, Dest | Performs bitwise XOR on Src1 and Src2 storing the result in Dest. | |
| 0x1F | NAND | Src1, Src2, Dest | Performs bitwise NAND on Src1 and Src2 storing the result in Dest. | |
| 0x20 | NOR | Src1, Src2, Dest | Performs bitwise NOR on Src1 and Src2 storing the result in Dest. | |
| 0x21 | XNOR | Src1, Src2, Dest | Performs bitwise XNOR on Src1 and Src2 storing the result in Dest. | |
| 0x22 | INT | Literal | Initiates an interrupt with the given 8 bit interrupt code. Triggering an interrupt invokes the following behaviour: The return address is saved to the RET register. The stack base ptr is set to the kernel stack. | |
| 0x23 | IRT | n/a | Returns from an interrupt. | |
| 0x24 | HLT | n/a | Halts the processor. | |
| 0x25 | IADD | Src1, Literal, Dest | An immediate version of addition taking a 16-bit immediate value. | |
| 0x26 | ISUB | Src1, Literal, Dest | An immediate version of subtraction taking a 16-bit immediate value. | |