diff --git a/Instruction-Set.md b/Instruction-Set.md index 99765fb..7232d14 100644 --- a/Instruction-Set.md +++ b/Instruction-Set.md @@ -54,44 +54,46 @@ To compute this address, the linker should find the address of the label, cut of ### Instructions # Processor Instruction Set Reference -| Hex | Mnemonic | Operands | Description | Type | -|------|----------|----------|-------------|------| -| 0x00 | NOP | n/a | No operation - a blank line. | | -| 0x01 | MOV | SrcReg, DestReg | Copies from SrcReg to DestReg. | | -| 0x02 | MOVS | SrcReg, DestReg | Copies from SrcReg to DestReg, sign extending the value to take up a full word. | | -| 0x03 | LDB | BaseReg, Offset, DestReg | Loads a byte from memory address (base + offset) into DestReg. The effective address must be byte-aligned. | | -| 0x04 | LDBS | BaseReg, Offset, DestReg | Loads a sign-extended byte from memory address (base + offset) into DestReg. The effective address must be byte-aligned. | | -| 0x05 | LDH | BaseReg, Offset, DestReg | Loads a half-word from memory address (base + offset) into DestReg. The effective address must be 2-byte-aligned. | | -| 0x06 | LDHS | BaseReg, Offset, DestReg | Loads a sign-extended half-word from memory address (base + offset) into DestReg. The effective address must be 2-byte-aligned. | | -| 0x07 | LDW | BaseReg, Offset, DestReg | Loads a word from memory address (base + offset) into DestReg. The effective address must be 4-byte-aligned. | | -| 0x08 | STB | SrcReg, BaseReg, Offset | Stores a byte from SrcReg in memory address (base + offset). The effective address must be byte-aligned. | | -| 0x09 | STH | SrcReg, BaseReg, Offset | Stores a half-word from SrcReg in memory address (base + offset). The effective address must be 2-byte-aligned. | | -| 0x0A | STW | SrcReg, BaseReg, Offset | Stores a word from SrcReg in memory address (base + offset). The effective address must be 4-byte-aligned. | | -| 0x0B | LLI | DstReg, Value | Loads a 16-bit literal value into reg, setting the bottom 16 bits of the word. To populate the upper 16 bits, see LUI. | | -| 0x0C | LUI | DstReg, Value | Loads a 16-bit literal value into reg, setting the top 16 bits of the word. To populate the lower 16 bits, see LLI. | | -| 0x0D | JMP | DestReg, Offset \| Address | Unconditionally jumps to the calculated address or direct address. | | -| 0x0E | JEQ | DestReg, Offset \| Address | Jumps to the calculated address or direct address if equal flag set. | | -| 0x0F | JNE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if the equal flag is not set. | | -| 0x10 | JGT | DestReg, Offset \| Address | Jumps to the calculated address or direct address if greater than flag set. | | -| 0x11 | JGE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if greater than flag or equal flag set. | | -| 0x12 | JLT | DestReg, Offset \| Address | Jumps to the calculated address or direct address if less than flag set. | | -| 0x13 | JLE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if less than flag or equal flag set. | | -| 0x14 | CMP | Reg1, Reg2 | Compares the value of Reg1 to the value in Reg2. The results of the comparisons are set in the Status register. | | -| 0x15 | INC | Reg | Increments the value in the given register. | | -| 0x16 | DEC | Reg | Decrements the value in the given register. | | -| 0x17 | SHL | Reg, Literal \| ValReg | Left shifts the value in Reg by the given amount (either a register, or a literal value). | | -| 0x18 | SHR | Reg, Literal \| ValReg | Right shifts the value in Reg by the given amount (either a register, or a literal value). | | -| 0x19 | ADD | Src1, Src2, Dest | Adds the value of Src2 to Src1 and writes the result to Dest. | | -| 0x1A | SUB | Src1, Src2, Dest | Subtracts the value of Src2 from Src1 and writes the result to Dest. | | -| 0x1B | AND | Src1, Src2, Dest | Performs bitwise AND on Src1 and Src2 storing the result in Dest. | | -| 0x1C | OR | Src1, Src2, Dest | Performs bitwise OR on Src1 and Src2 storing the result in Dest. | | -| 0x1D | NOT | Src, Dest | Performs bitwise NOT on Src storing the result in Dest. | | -| 0x1E | XOR | Src1, Src2, Dest | Performs bitwise XOR on Src1 and Src2 storing the result in Dest. | | -| 0x1F | NAND | Src1, Src2, Dest | Performs bitwise NAND on Src1 and Src2 storing the result in Dest. | | -| 0x20 | NOR | Src1, Src2, Dest | Performs bitwise NOR on Src1 and Src2 storing the result in Dest. | | -| 0x21 | XNOR | Src1, Src2, Dest | Performs bitwise XNOR on Src1 and Src2 storing the result in Dest. | | -| 0x22 | INT | Literal | Initiates an interrupt with the given 8 bit interrupt code. Triggering an interrupt invokes the following behaviour: The return address is saved to the RET register. The stack base ptr is set to the kernel stack. | | -| 0x23 | IRT | n/a | Returns from an interrupt. | | -| 0x24 | HLT | n/a | Halts the processor. | | -| 0x25 | IADD | Src1, Literal, Dest | An immediate version of addition taking a 16-bit immediate value. | | -| 0x26 | ISUB | Src1, Literal, Dest | An immediate version of subtraction taking a 16-bit immediate value. | | +# Processor Instruction Set Reference + +| Hex | Type | Mnemonic | Operands | Description | +|------|------|----------|----------|-------------| +| 0x00 | R | NOP | n/a | No operation - a blank line. | +| 0x01 | R | MOV | SrcReg, DestReg | Copies from SrcReg to DestReg. | +| 0x02 | R | MOVS | SrcReg, DestReg | Copies from SrcReg to DestReg, sign extending the value to take up a full word. | +| 0x03 | R | LDB | BaseReg, Offset, DestReg | Loads a byte from memory address (base + offset) into DestReg. The effective address must be byte-aligned. | +| 0x04 | R | LDBS | BaseReg, Offset, DestReg | Loads a sign-extended byte from memory address (base + offset) into DestReg. The effective address must be byte-aligned. | +| 0x05 | R | LDH | BaseReg, Offset, DestReg | Loads a half-word from memory address (base + offset) into DestReg. The effective address must be 2-byte-aligned. | +| 0x06 | R | LDHS | BaseReg, Offset, DestReg | Loads a sign-extended half-word from memory address (base + offset) into DestReg. The effective address must be 2-byte-aligned. | +| 0x07 | R | LDW | BaseReg, Offset, DestReg | Loads a word from memory address (base + offset) into DestReg. The effective address must be 4-byte-aligned. | +| 0x08 | R | STB | SrcReg, BaseReg, Offset | Stores a byte from SrcReg in memory address (base + offset). The effective address must be byte-aligned. | +| 0x09 | R | STH | SrcReg, BaseReg, Offset | Stores a half-word from SrcReg in memory address (base + offset). The effective address must be 2-byte-aligned. | +| 0x0A | R | STW | SrcReg, BaseReg, Offset | Stores a word from SrcReg in memory address (base + offset). The effective address must be 4-byte-aligned. | +| 0x0B | I | LLI | DstReg, Value | Loads a 16-bit literal value into reg, setting the bottom 16 bits of the word. To populate the upper 16 bits, see LUI. | +| 0x0C | I | LUI | DstReg, Value | Loads a 16-bit literal value into reg, setting the top 16 bits of the word. To populate the lower 16 bits, see LLI. | +| 0x0D | J | JMP | DestReg, Offset \| Address | Unconditionally jumps to the calculated address or direct address. | +| 0x0E | J | JEQ | DestReg, Offset \| Address | Jumps to the calculated address or direct address if equal flag set. | +| 0x0F | J | JNE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if the equal flag is not set. | +| 0x10 | J | JGT | DestReg, Offset \| Address | Jumps to the calculated address or direct address if greater than flag set. | +| 0x11 | J | JGE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if greater than flag or equal flag set. | +| 0x12 | J | JLT | DestReg, Offset \| Address | Jumps to the calculated address or direct address if less than flag set. | +| 0x13 | J | JLE | DestReg, Offset \| Address | Jumps to the calculated address or direct address if less than flag or equal flag set. | +| 0x14 | R | CMP | Reg1, Reg2 | Compares the value of Reg1 to the value in Reg2. The results of the comparisons are set in the Status register. | +| 0x15 | R | INC | Reg | Increments the value in the given register. | +| 0x16 | R | DEC | Reg | Decrements the value in the given register. | +| 0x17 | I | SHL | Reg, Literal \| ValReg | Left shifts the value in Reg by the given amount (either a register, or a literal value). | +| 0x18 | I | SHR | Reg, Literal \| ValReg | Right shifts the value in Reg by the given amount (either a register, or a literal value). | +| 0x19 | R | ADD | Src1, Src2, Dest | Adds the value of Src2 to Src1 and writes the result to Dest. | +| 0x1A | R | SUB | Src1, Src2, Dest | Subtracts the value of Src2 from Src1 and writes the result to Dest. | +| 0x1B | R | AND | Src1, Src2, Dest | Performs bitwise AND on Src1 and Src2 storing the result in Dest. | +| 0x1C | R | OR | Src1, Src2, Dest | Performs bitwise OR on Src1 and Src2 storing the result in Dest. | +| 0x1D | R | NOT | Src, Dest | Performs bitwise NOT on Src storing the result in Dest. | +| 0x1E | R | XOR | Src1, Src2, Dest | Performs bitwise XOR on Src1 and Src2 storing the result in Dest. | +| 0x1F | R | NAND | Src1, Src2, Dest | Performs bitwise NAND on Src1 and Src2 storing the result in Dest. | +| 0x20 | R | NOR | Src1, Src2, Dest | Performs bitwise NOR on Src1 and Src2 storing the result in Dest. | +| 0x21 | R | XNOR | Src1, Src2, Dest | Performs bitwise XNOR on Src1 and Src2 storing the result in Dest. | +| 0x22 | I | INT | Literal | Initiates an interrupt with the given 8 bit interrupt code. Triggering an interrupt invokes the following behaviour: The return address is saved to the RET register. The stack base ptr is set to the kernel stack. | +| 0x23 | R | IRT | n/a | Returns from an interrupt. | +| 0x24 | R | HLT | n/a | Halts the processor. | +| 0x25 | I | IADD | Src1, Literal, Dest | An immediate version of addition taking a 16-bit immediate value. | +| 0x26 | I | ISUB | Src1, Literal, Dest | An immediate version of subtraction taking a 16-bit immediate value. |