zxq5/damn_simple_architecture
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renamed NoReg to Null in common

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zxq5
2026-02-09 00:04:19 +00:00
parent 328741eb51
commit f7ed764e96
3 changed files with 12 additions and 12 deletions
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common/src/instructions/encode/tests.rs
+4 -4
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@@ -2,7 +2,7 @@ use crate::prelude::*;
#[test]
fn test_encode_nop() {
let no_reg = Register::NoReg as u32;
let no_reg = Register::Null as u32;
let no_op = u32::from(Instruction::Nop.opcode());
let expected = (no_op << 26) | (no_reg << 21) | (no_reg << 16) | (no_reg << 11);
@@ -15,7 +15,7 @@ fn test_encode_nop() {
fn test_encode_mov() {
let rg0 = Register::Rg0 as u32;
let rg1 = Register::Rg1 as u32;
let no_reg = Register::NoReg as u32;
let no_reg = Register::Null as u32;
let instruction = Instruction::Mov(RTypeArgs::new(
Some(Register::Rg0),
@@ -53,7 +53,7 @@ fn test_encode_load_byte() {
#[test]
fn test_encode_shift_left_shamt() {
let rg0 = Register::Rg0 as u32;
let no_reg = Register::NoReg as u32;
let no_reg = Register::Null as u32;
let shift_amount = 5;
@@ -80,7 +80,7 @@ fn test_encode_shift_left_shamt() {
fn test_encode_shift_left_reg() {
let rg0 = Register::Rg0 as u32;
let rg1 = Register::Rg1 as u32;
let no_reg = Register::NoReg as u32;
let no_reg = Register::Null as u32;
let instruction = Instruction::ShiftLeft(RTypeArgs::new(
Some(Register::Rg0),