renamed NoReg to Null in common

common/src/instructions.rs

@@ -69,7 +69,7 @@ pub enum Register {
     Idr,
     Mmr,
     Zero,
-    NoReg,
+    Null, // Invalid - Triggers a fault if accessed
 
     // system registers - can't be written to by instructions.
     Mar,
@@ -106,7 +106,7 @@ impl Register {
 
 impl Default for Register {
     fn default() -> Self {
-        Self::NoReg
+        Self::Null
     }
 }
 
@@ -144,7 +144,7 @@ impl TryFrom<u8> for Register {
             0x14 => Self::Idr,
             0x15 => Self::Mmr,
             0x16 => Self::Zero,
-            0x17 => Self::NoReg,
+            0x17 => Self::Null,
             0x18 => Self::Mar,
             0x19 => Self::Mdr,
             0x1A => Self::Sts,
@@ -183,7 +183,7 @@ impl TryFrom<&str> for Register {
             "idr" => Ok(Self::Idr),
             "mmr" => Ok(Self::Mmr),
             "zero" => Ok(Self::Zero),
-            "null" => Ok(Self::NoReg),
+            "null" => Ok(Self::Null),
             "pcx" => Ok(Self::Pcx),
             _ => Err(RegisterParseError::InvalidName(value.to_string())),
         }
@@ -216,7 +216,7 @@ impl std::fmt::Display for Register {
             Self::Idr => write!(f, "idr"),
             Self::Mmr => write!(f, "mmr"),
             Self::Zero => write!(f, "zero"),
-            Self::NoReg => write!(f, "noreg"),
+            Self::Null => write!(f, "null"),
             Self::Mar => write!(f, "mar"),
             Self::Mdr => write!(f, "mdr"),
             Self::Sts => write!(f, "sts"),

common/src/instructions/encode.rs

@@ -8,9 +8,9 @@ pub trait Encode {
 /// Encodes a zero argument instruction.
 fn encode_no_args(opcode: u8) -> u32 {
     let opcode = u32::from(opcode);
-    let sr1 = Register::NoReg as u32;
-    let sr2 = Register::NoReg as u32;
-    let dr = Register::NoReg as u32;
+    let sr1 = Register::Null as u32;
+    let sr2 = Register::Null as u32;
+    let dr = Register::Null as u32;
     let shamt = 0;
 
     (opcode << 26) | (sr1 << 21) | (sr2 << 16) | (dr << 11) | (shamt << 6)

common/src/instructions/encode/tests.rs

@@ -2,7 +2,7 @@ use crate::prelude::*;
 
 #[test]
 fn test_encode_nop() {
-    let no_reg = Register::NoReg as u32;
+    let no_reg = Register::Null as u32;
     let no_op = u32::from(Instruction::Nop.opcode());
 
     let expected = (no_op << 26) | (no_reg << 21) | (no_reg << 16) | (no_reg << 11);
@@ -15,7 +15,7 @@ fn test_encode_nop() {
 fn test_encode_mov() {
     let rg0 = Register::Rg0 as u32;
     let rg1 = Register::Rg1 as u32;
-    let no_reg = Register::NoReg as u32;
+    let no_reg = Register::Null as u32;
 
     let instruction = Instruction::Mov(RTypeArgs::new(
         Some(Register::Rg0),
@@ -53,7 +53,7 @@ fn test_encode_load_byte() {
 #[test]
 fn test_encode_shift_left_shamt() {
     let rg0 = Register::Rg0 as u32;
-    let no_reg = Register::NoReg as u32;
+    let no_reg = Register::Null as u32;
 
     let shift_amount = 5;
 
@@ -80,7 +80,7 @@ fn test_encode_shift_left_shamt() {
 fn test_encode_shift_left_reg() {
     let rg0 = Register::Rg0 as u32;
     let rg1 = Register::Rg1 as u32;
-    let no_reg = Register::NoReg as u32;
+    let no_reg = Register::Null as u32;
 
     let instruction = Instruction::ShiftLeft(RTypeArgs::new(
         Some(Register::Rg0),