- updated assembler to support new shift implementation

- updated emulator to support new shift implementation
- updated emulator to rename NoReg to Null as in the common lib

emulator/src/emulator/system/model.rs

@@ -286,7 +286,7 @@ impl RegFile {
             Register::Sts => &mut self.sts,
             Register::Cir => &mut self.cir,
             Register::Pcx => &mut self.pcx,
-            _ => return Err(ProcessorError::InvalidRegister(Register::NoReg as u8)),
+            _ => return Err(ProcessorError::InvalidRegister(Register::Null as u8)),
         })
     }
 
@@ -321,7 +321,7 @@ impl RegFile {
             Register::Cir => self.cir,
             Register::Pcx => self.pcx,
             Register::Zero => 0,
-            _ => return Err(ProcessorError::InvalidRegister(Register::NoReg as u8)),
+            _ => return Err(ProcessorError::InvalidRegister(Register::Null as u8)),
         })
     }
 }

emulator/src/emulator/system/processor/mod.rs

@@ -349,17 +349,13 @@ impl Executable for Instruction {
             // Left shifts the value in Reg by the given amount (either a register, or a
             // literal value)
             Self::ShiftLeft(a) => {
-                let reg = cpu.get(a.sr1)?;
-                let val = a.shamt;
-                *cpu.reg(a.sr1)? = shl(reg, val);
+                *cpu.reg(a.dr)? = shl(cpu.get(a.sr1)?, a.shamt + cpu.get(a.sr2)? as u8);
             }
 
             // Right shifts the value in Reg by the given amount (either a register, or a
             // literal value).
             Self::ShiftRight(a) => {
-                let regval = cpu.get(a.sr1)?;
-                let val = a.shamt;
-                *cpu.reg(a.sr1)? = shr(regval, val);
+                *cpu.reg(a.dr)? = shr(cpu.get(a.sr1)?, a.shamt + cpu.get(a.sr2)? as u8);
             }
 
             // Adds the value of Src2 to Src1 and writes the result to a.dr