fixed some clippy errors

common/src/instructions.rs

@@ -414,8 +414,8 @@ impl std::fmt::Display for Instruction {
 
             Self::Increment(a) | Self::Decrement(a) => write!(f, " {}", a.sr1),
             Self::Interrupt(a) => write!(f, " {}", a.as_u8()),
-            Self::Data(a) => write!(f, " {}", a),
-            Self::Segment(x) => write!(f, " [SEGMENT {}]", x),
+            Self::Data(a) => write!(f, " {a}"),
+            Self::Segment(x) => write!(f, " [SEGMENT {x}]"),
             _ => Ok(()),
         }
     }
@@ -469,7 +469,7 @@ impl TryFrom<u32> for Instruction {
             0x24 => Ok(Self::Halt),
             0x25 => Ok(Self::AddImmediate(ITypeArgs::try_from(data)?)),
             0x26 => Ok(Self::SubImmediate(ITypeArgs::try_from(data)?)),
-            0x3F => Ok(Self::Segment(data as u8 as u32)),
+            0x3F => Ok(Self::Segment(u32::from(data as u8))),
             _ => Err(InstructionDecodeError::InvalidOpcode(opcode)),
         }
     }

common/src/instructions/encode.rs

@@ -58,7 +58,7 @@ impl Encode for Instruction {
                 Self::Segment(segment) => {
                     let opcode = u32::from(self.opcode());
                     let segment = segment as u8;
-                    (opcode << 26) | (segment as u32)
+                    (opcode << 26) | u32::from(segment)
                 }
             ]
         )

common/src/instructions/encode/tests.rs

@@ -5,7 +5,7 @@ fn test_encode_nop() {
     let no_reg = Register::NoReg as u32;
     let no_op = u32::from(Instruction::Nop.opcode());
 
-    let expected = no_op << 26 | no_reg << 21 | no_reg << 16 | no_reg << 11;
+    let expected = (no_op << 26) | (no_reg << 21) | (no_reg << 16) | (no_reg << 11);
     let got = Instruction::Nop.encode();
 
     assert_eq!(expected, got);
@@ -25,7 +25,7 @@ fn test_encode_mov() {
     ));
     let mov = u32::from(instruction.opcode());
 
-    let expected = mov << 26 | rg0 << 21 | no_reg << 16 | rg1 << 11;
+    let expected = (mov << 26) | (rg0 << 21) | (no_reg << 16) | (rg1 << 11);
     let got = instruction.encode();
 
     assert_eq!(expected, got);
@@ -44,7 +44,7 @@ fn test_encode_load_byte() {
     ));
     let load_byte = u32::from(instruction.opcode());
 
-    let expected = load_byte << 26 | rg0 << 21 | rg1 << 16 | u32::from(immediate);
+    let expected = (load_byte << 26) | (rg0 << 21) | (rg1 << 16) | u32::from(immediate);
     let got = instruction.encode();
 
     assert_eq!(expected, got);
@@ -65,8 +65,11 @@ fn test_encode_shift_left_shamt() {
     ));
     let shift_left = u32::from(instruction.opcode());
 
-    let expected =
-        shift_left << 26 | rg0 << 21 | no_reg << 16 | no_reg << 11 | u32::from(shift_amount) << 6;
+    let expected = (shift_left << 26)
+        | (rg0 << 21)
+        | (no_reg << 16)
+        | (no_reg << 11)
+        | (u32::from(shift_amount) << 6);
 
     let got = instruction.encode();
 
@@ -87,7 +90,7 @@ fn test_encode_shift_left_reg() {
     ));
     let shift_left = u32::from(instruction.opcode());
 
-    let expected = shift_left << 26 | rg0 << 21 | rg1 << 16 | no_reg << 11;
+    let expected = (shift_left << 26) | (rg0 << 21) | (rg1 << 16) | (no_reg << 11);
 
     let got = instruction.encode();