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- fixed some clippy lints

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- updated comments in compiler codegen
- deleted old dsa compiler outputs
- settings for zed
This commit is contained in:
zxq5
2026-02-14 11:05:15 +00:00
parent 201b18069b
commit 7ccbd9258f
16 changed files with 138 additions and 641 deletions
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.zed/settings.json
+15
View File
@@ -0,0 +1,15 @@
// Folder-specific settings
//
// For a full list of overridable settings, and general information on folder-specific settings,
// see the documentation: https://zed.dev/docs/configuring-zed#settings-files
{
"lsp": {
"rust-analyzer": {
"initialization_options": {
"check": {
"command": "clippy", // rust-analyzer.check.command (default: "check")
},
},
},
},
}
assembler/src/assembler/model.rs
+5 -5
View File
@@ -184,11 +184,11 @@ pub enum Token {
impl fmt::Display for Token {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
match self {
Self::Symbol(symbol) => write!(f, "{}", symbol),
Self::Register(register) => write!(f, "{}", register),
Self::Immediate(immediate) => write!(f, "{}", immediate),
Self::StringLit(string_lit) => write!(f, "{}", string_lit),
Self::Opcode(opcode) => write!(f, "{}", opcode),
Self::Symbol(symbol) => write!(f, "{symbol}"),
Self::Register(register) => write!(f, "{register}",),
Self::Immediate(immediate) => write!(f, "{immediate}",),
Self::StringLit(string_lit) => write!(f, "{string_lit}",),
Self::Opcode(opcode) => write!(f, "{opcode}",),
}
}
}
assembler/src/assembler/parser.rs
+12 -10
View File
@@ -101,6 +101,7 @@ impl Parser {
let opcode = expect_token!(self.next()?, Opcode)?;
let args: Vec<Token>;
#[allow(clippy::match_same_arms)]
match opcode {
// R-type instructions
Opcode::Mov | Opcode::Movs => {
@@ -113,24 +114,25 @@ impl Parser {
let base = expect_type!(self.next()?, Register, Symbol)?;
let dest = expect_type!(self.next()?, Register)?;
let mut offset = Token::Immediate(0);
if let Ok(next) = self.peek_next()
&& expect_type!(next, Immediate).is_ok()
{
offset = self.next()?;
let offset = match self.peek_next() {
Ok(next) if expect_type!(next.clone(), Immediate).is_ok() => {
self.next()?
}
_ => Token::Immediate(0),
};
args = vec![base, dest, offset];
}
Opcode::Stb | Opcode::Sth | Opcode::Stw => {
let base = expect_type!(self.next()?, Register)?;
let dest = expect_type!(self.next()?, Register, Symbol)?;
let mut offset = Token::Immediate(0);
if let Ok(next) = self.peek_next()
&& expect_type!(next, Immediate).is_ok()
{
offset = self.next()?;
let offset = match self.peek_next() {
Ok(next) if expect_type!(next.clone(), Immediate).is_ok() => {
self.next()?
}
_ => Token::Immediate(0),
};
args = vec![base, dest, offset];
}
assembler/src/lib.rs
+1 -1
View File
@@ -34,7 +34,7 @@ use crate::prelude::CompilerEngine;
pub fn assemble_file(input: &str, output: &str) -> Result<(), std::io::Error> {
let mut engine = CompilerEngine::new();
engine.start_compilation(Path::new(input));
let result = engine.wait_for_result().unwrap();
let result = engine.wait_for_result().expect("assembler failed.");
let buffer: Vec<u8> = result
.iter()
common/src/instructions.rs
+3 -7
View File
@@ -40,7 +40,7 @@ pub enum InstructionType {
Immediate,
}
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
#[derive(Copy, Clone, Debug, PartialEq, Eq, Default)]
#[non_exhaustive]
pub enum Register {
// general purpose registers
@@ -69,6 +69,8 @@ pub enum Register {
Idr,
Mmr,
Zero,
#[default]
Null, // Invalid - Triggers a fault if accessed
// system registers - can't be written to by instructions.
@@ -104,12 +106,6 @@ impl Register {
}
}
impl Default for Register {
fn default() -> Self {
Self::Null
}
}
impl TryFrom<u8> for Register {
type Error = RegisterParseError;
compiler/src/backend/dsa/codegen.rs
+49 -56
View File
@@ -83,34 +83,27 @@ impl CodeGenerator {
let mut block = IB::new();
block.extend(vec![
I::comment("GENERATED BY DSC COMPILER"),
I::comment(format!(
"Generated at {}\n",
I::global_comment(format!(
"GENERATED BY DSC COMPILER
Generated at {}",
datetime.format("%Y-%m-%d %H:%M:%S")
)),
I::comment("Imports"),
I::Newline,
I::global_comment("Imports"),
]);
block.extend(
self.imports
.iter()
.map(|(_name, instruction)| instruction.clone())
.collect::<Vec<_>>(),
);
block.push(I::comment(""));
block.push(I::comment("Globals & Reserved Memory"));
block.extend(
self.globals
.iter()
.map(|(_name, instruction)| instruction.clone())
.collect::<Vec<_>>(),
);
block.extend(self.imports.values().cloned().collect::<Vec<_>>());
block.extend(vec![
I::comment(""),
I::comment("Entry Point"),
I::Newline,
I::global_comment("Globals & Reserved Memory"),
]);
block.extend(self.globals.values().cloned().collect::<Vec<_>>());
block.extend(vec![
I::Newline,
I::global_comment("Entry Point"),
I::db_word("stack", 0x10000),
I::db_string("message", "Process Exited with code:"),
// init function for stack setup.
@@ -127,8 +120,9 @@ impl CodeGenerator {
I::call("print::print_hex_word"),
I::pop(Register::Zero),
I::Hlt,
I::Newline,
// default return block boilerplate
I::comment("Return"),
I::global_comment("Return"),
I::label("_ret"),
I::mov(Register::Bpr, Register::Spr),
I::pop(Register::Bpr),
@@ -199,11 +193,8 @@ impl CodeGenerator {
.collect::<Vec<String>>()
.join(", ");
code.push(I::comment(format!(
"fn {name}({fmtparams}) -> {return_type}"
)));
code.extend(vec![
I::global_comment(format!("fn {name}({fmtparams}) -> {return_type}")),
I::label(name),
I::push(Register::Bpr),
I::mov(Register::Spr, Register::Bpr),
@@ -233,6 +224,8 @@ impl CodeGenerator {
code.push(I::jmp("_ret"));
}
code.insert(0, I::Newline);
code
}
@@ -336,19 +329,19 @@ impl CodeGenerator {
I::sub(var_reg, result_reg, temp_reg)
}
AssignmentOperator::MulAssign => {
return Err(CompilerError::Unimplemented(format!(
"TODO: implement multiplication for assignment"
)));
return Err(CompilerError::Unimplemented(
"TODO: implement multiplication for assignment".to_string(),
));
}
AssignmentOperator::DivAssign => {
return Err(CompilerError::Unimplemented(format!(
"TODO: write proper div function for DSA"
)));
return Err(CompilerError::Unimplemented(
"TODO: write proper div function for DSA".to_string(),
));
}
AssignmentOperator::ModAssign => {
return Err(CompilerError::Unimplemented(format!(
"TODO: write proper mod function for DSA"
)));
return Err(CompilerError::Unimplemented(
"TODO: write proper mod function for DSA".to_string(),
));
}
AssignmentOperator::AndAssign => {
I::and(var_reg, result_reg, temp_reg)
@@ -428,7 +421,7 @@ impl CodeGenerator {
code.append(self.generate_statement(s, func_body)?);
}
if then_stmt.len() == 0 {
if then_stmt.is_empty() {
code.push(I::Nop);
}
@@ -440,7 +433,7 @@ impl CodeGenerator {
code.append(self.generate_statement(s, func_body)?);
}
if else_stmt.len() == 0 {
if else_stmt.is_empty() {
code.push(I::Nop);
}
@@ -620,9 +613,9 @@ impl CodeGenerator {
code.push(I::pop(Register::Zero));
}
BinaryOperator::Div => {
return Err(CompilerError::Unimplemented(format!(
"TODO: write proper div function for DSA"
)));
return Err(CompilerError::Unimplemented(
"TODO: write proper div function for DSA".to_string(),
));
// self.include("maths", "./lib/maths/core.dsa");
// // Call divide function
// code.push(format!("\tpush {}", right_reg));
@@ -632,9 +625,9 @@ impl CodeGenerator {
// code.push("\tpop zero".to_string());
}
BinaryOperator::Mod => {
return Err(CompilerError::Unimplemented(format!(
"TODO: write proper mod function for DSA"
)));
return Err(CompilerError::Unimplemented(
"TODO: write proper mod function for DSA".to_string(),
));
// self.include("maths", "./lib/maths/core.dsa");
// // Call modulo function
// code.push(format!("\tpush {}", right_reg));
@@ -653,14 +646,14 @@ impl CodeGenerator {
code.push(I::xor(left_reg, right_reg, result_reg));
}
BinaryOperator::LogicalAnd => {
return Err(CompilerError::Unimplemented(format!(
"assembler/ISA does not yet support logical and!"
)));
return Err(CompilerError::Unimplemented(
"assembler/ISA does not yet support logical and!".to_string(),
));
}
BinaryOperator::LogicalOr => {
return Err(CompilerError::Unimplemented(format!(
"assembler/ISA does not yet support logical or!"
)));
return Err(CompilerError::Unimplemented(
"assembler/ISA does not yet support logical or!".to_string(),
));
}
BinaryOperator::LeftShift => {
code.push(I::shl(left_reg, right_reg, 0, result_reg));
@@ -816,9 +809,9 @@ impl CodeGenerator {
code.push(I::not(operand_reg, result_reg));
}
UnaryOperator::LogicalNot => {
return Err(CompilerError::Unimplemented(format!(
"Assembler/ISA does not yet support logical not"
)));
return Err(CompilerError::Unimplemented(
"Assembler/ISA does not yet support logical not".to_string(),
));
}
_ => {
return Err(CompilerError::Generic(format!(
@@ -932,9 +925,9 @@ impl CodeGenerator {
expr,
field_name,
type_id,
} => Err(CompilerError::Unimplemented(format!(
"Structs are not yet implemented!"
))),
} => Err(CompilerError::Unimplemented(
"Structs are not yet implemented!".to_string(),
)),
Expression::TypeCast {
expr,
compiler/src/backend/dsa/instruction.rs
+33 -5
View File
@@ -60,7 +60,11 @@ impl From<Instruction> for InsBlock {
pub enum Instruction {
// Labels and comments
Label(Label),
Comment(String),
Comment {
text: String,
top_level: bool,
},
Newline,
// Data Directives
Db {
@@ -287,7 +291,20 @@ impl fmt::Display for Instruction {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self {
Self::Label(l) => write!(f, "{}:", l),
Self::Comment(c) => write!(f, "// {}", c),
Self::Newline => write!(f, ""), /* empty string as newlines are inserted */
// automatically.
Self::Comment { text, top_level } => write!(
f,
"{}",
text.lines()
.map(|line| format!(
"{}// {}",
if *top_level { "" } else { " " },
line.trim(),
))
.collect::<Vec<String>>()
.join("\n")
),
Self::Include { name, path } => write!(f, "include {name}: \"{}\"", path),
@@ -455,6 +472,7 @@ impl fmt::Display for Instruction {
}
}
}
impl Instruction {
// data directives
pub fn db_string(label: impl Into<String>, data: impl Into<String>) -> Self {
@@ -590,7 +608,7 @@ impl Instruction {
}
pub fn iadd(src: Register, value: i64) -> Self {
let imm = Imm(value.abs() as u32);
let imm = Imm(value.unsigned_abs() as u32);
if value < 0 {
Self::ISub {
@@ -608,7 +626,7 @@ impl Instruction {
}
pub fn iadd_dest(src: Register, value: i32, dest: Register) -> Self {
let imm = Imm(value.abs() as u32);
let imm = Imm(value.unsigned_abs());
if value < 0 {
Self::ISub {
@@ -702,7 +720,17 @@ impl Instruction {
// Utilities
pub fn comment(text: impl Into<String>) -> Self {
Self::Comment(text.into())
Self::Comment {
text: text.into(),
top_level: false,
}
}
pub fn global_comment(text: impl Into<String>) -> Self {
Self::Comment {
text: text.into(),
top_level: true,
}
}
pub fn include(name: impl Into<String>, path: impl Into<String>) -> Self {
compiler/src/backend/dsa/registers.rs
+7 -19
View File
@@ -186,8 +186,7 @@ impl RegisterAllocator {
// Update location to register
self.variable_locations
.insert(var_name.to_string(), location);
self.register_contents
.insert(reg.clone(), var_name.to_string());
self.register_contents.insert(reg, var_name.to_string());
return Ok((reg, code));
}
@@ -197,8 +196,7 @@ impl RegisterAllocator {
let (reg, code) = self.alloc_temp()?;
self.variable_locations
.insert(var_name.to_string(), Location::register(reg));
self.register_contents
.insert(reg.clone(), var_name.to_string());
self.register_contents.insert(reg, var_name.to_string());
Ok((reg, code))
}
@@ -225,11 +223,12 @@ impl RegisterAllocator {
// Check if variable already has a location
if let Some(location) = self.variable_locations.get(var_name) {
// if the variable exists in a register we write to that.
if let Some(reg) = location.register {
if reg == *source_reg {
match location.register {
Some(reg) if reg == *source_reg => {
block.push(Instruction::mov(*source_reg, reg));
return block;
}
_ => (),
}
// if the variable exists on the stack but not a register we write here.
@@ -263,7 +262,7 @@ impl RegisterAllocator {
self.variable_locations
.insert(var_name.to_string(), Location::register(free_reg));
self.register_contents
.insert(free_reg.clone(), var_name.to_string());
.insert(free_reg, var_name.to_string());
self.in_use[free_reg as usize].1 = true;
block.push(Instruction::mov(*source_reg, free_reg));
@@ -428,17 +427,6 @@ impl RegisterAllocator {
.collect();
}
/// Mark a variable as dead (no longer needed)
/// Frees its register if it's in one
// pub fn _free_var(&mut self, var_name: &str) {
// if let Some(Location::Register(reg)) = self.variable_locations.get(var_name) {
// let reg = reg.clone();
// self.register_contents.remove(&reg);
// self.in_use.insert(reg, false);
// }
// self.variable_locations.remove(var_name);
// }
/// Get list of registers that contain variables and are in use
/// These need to be saved before function calls
pub fn get_caller_saved_registers(&self) -> Vec<Register> {
@@ -450,7 +438,7 @@ impl RegisterAllocator {
.unwrap_or(&(Register::Null, false))
.1
})
.map(|(reg, _)| reg.clone())
.map(|(reg, _)| *reg)
.collect()
}
}
compiler/src/frontend/dsc/lexer.rs
+7 -6
View File
@@ -592,8 +592,7 @@ impl<'a> Lexer<'a> {
if c.is_ascii_digit() {
self.advance();
num_str.push(c);
} else if c == '_'
&& self.peek_second().map_or(false, |ch| ch.is_ascii_digit())
} else if c == '_' && self.peek_second().is_some_and(|ch| ch.is_ascii_digit())
{
// Allow underscores as separators only between digits
self.advance();
@@ -611,10 +610,11 @@ impl<'a> Lexer<'a> {
let mut num_str = String::new();
// Read the first hex digit (current character)
if let Some(c) = self.current {
if c.is_ascii_hexdigit() {
match self.current {
Some(c) if c.is_ascii_hexdigit() => {
num_str.push(c);
}
_ => (),
}
while let Some(c) = self.peek() {
@@ -640,10 +640,11 @@ impl<'a> Lexer<'a> {
let mut num_str = String::new();
// Read the first binary digit (current character)
if let Some(c) = self.current {
if c == '0' || c == '1' {
match self.current {
Some(c) if c == '0' || c == '1' => {
num_str.push(c);
}
_ => (),
}
while let Some(c) = self.peek() {
compiler/src/frontend/dsc/parser.rs
+2 -2
View File
@@ -123,7 +123,7 @@ impl Parser {
}
let _ = expect_tt!(self.next()?, RightBrace)?;
return ParseResult::Accept(Declaration::Struct { name, fields });
ParseResult::Accept(Declaration::Struct { name, fields })
}
fn parse_func(&mut self) -> ParseResult<Declaration, CompilerError> {
@@ -403,7 +403,7 @@ impl Parser {
let expr = self.parse_expression()?;
let _ = expect_tt!(self.next()?, Semicolon)?;
return ParseResult::Accept(Statement::Expression { expr });
ParseResult::Accept(Statement::Expression { expr })
}
fn parse_expression(&mut self) -> ParseResult<Expression, CompilerError> {
compiler/src/main.rs
-2
View File
@@ -1,7 +1,5 @@
use std::path::Path;
use compiler;
fn main() {
// read from input file: syntax "c_compiler <src.c> [output.dsa]"
let args: Vec<String> = std::env::args().collect();
resources/dsa/example.dsa
-119
View File
@@ -1,119 +0,0 @@
// GENERATED BY DSC COMPILER
// Generated at 2026-02-14 02:44:56
// Imports
include arena: "./lib/memory/arena_alloc.dsa"
include print: "./lib/io/print.dsa"
//
// Globals & Reserved Memory
//
// Entry Point
dw stack: 0x010000
db message: "Process Exited with code:"
_init:
ldw stack, bpr, 0
mov bpr, spr
push zero
call main
call print::print_newline
lwi message, rg0
push rg0
call print::print
pop zero
call print::print_hex_word
pop zero
hlt
// Return
_ret:
mov bpr, spr
pop bpr
return
db str_1: "end"
// fn main() -> u32
main:
push bpr
mov spr, bpr
lli 0, rg0
push rg0
addi spr, 0, rg1
lli 512, rg0
push rg1
// push arg 0
push rg0
call arena::new
pop rg2
lli 32, rg0
push rg2
// push arg 1
push rg0
// push arg 0
push rg2
call arena::alloc
pop rg3
pop zero
lli 32, rg0
ldw spr, rg2, 0
push rg3
stw rg2, spr, 4
// push arg 1
push rg0
// push arg 0
push rg2
call arena::alloc
pop rg4
pop zero
ldw spr, rg0, 4
stw rg0, spr, 4
push rg4
// push arg 0
push rg0
call print::print_hex_word
pop zero
call print::print_newline
ldw spr, rg0, 4
stw rg0, spr, 4
// push arg 0
push rg0
call print::print_hex_word
pop zero
call print::print_newline
ldw spr, rg0, 0
stw rg0, spr, 0
// push arg 0
push rg0
call print::print_hex_word
pop zero
call print::print_newline
ldw spr, rg0, 0
ldw rg0, rg2, 0
stw rg0, spr, 0
// push arg 0
push rg2
call print::print_num
pop zero
call print::print_newline
lli 42, rg2
ldw spr, rg5, 0
stw rg2, rg5, 0
stw rg5, spr, 0
// push arg 0
push rg5
call print::print_hex_word
pop zero
call print::print_newline
ldw spr, rg2, 0
ldw rg2, rg5, 0
stw rg2, spr, 0
// push arg 0
push rg5
call print::print_num
pop zero
call print::print_newline
lwi str_1, rg5
// push arg 0
push rg5
call print::println
pop zero
lli 0, rg5
stw rg5, bpr, 8
jmp _ret
resources/dsa/main.dsa
-141
View File
@@ -1,141 +0,0 @@
// GENERATED BY DSC COMPILER
// Generated at 2026-02-10 19:36:18
// Imports
include alloc: "./lib/memory/block_alloc.dsa"
include print: "./lib/io/print.dsa"
//
// Globals & Reserved Memory
//
// Entry Point
dw stack: 0x010000
db message: "Process Exited with code:"
_init:
ldw stack, bpr 0
mov bpr, spr
push zero
call main
call print::print_newline
lwi message, rg0
push rg0
call print::print
pop zero
call print::print_hex_word
pop zero
hlt
// Return
_ret:
mov bpr, spr
pop bpr
return
db str_5: "successful free of ptr"
// fn main() -> u32
main:
push bpr
mov spr, bpr
lli 32, rg0
lli 64, rg1
// push arg 1
push rg0
// push arg 0
push rg1
call alloc::init
pop rg2
pop zero
push rg2
// push arg 0
push rg2
call print::print_hex_word
pop zero
call print::print_newline
ldw spr, rg0 0
stw rg0, spr 0
// push arg 0
push rg0
call alloc::alloc
pop rg1
push rg1
// push arg 0
push rg1
call print::print_hex_word
pop zero
lli 200, rg0
ldw spr, rg1 0
stw rg0, rg1 0
stw rg1, spr 0
call print::print_newline
ldw spr, rg0 4
stw rg0, spr 4
// push arg 0
push rg0
call alloc::alloc
pop rg2
push rg2
// push arg 0
push rg2
call print::print_hex_word
pop zero
call print::print_newline
ldw spr, rg0 4
ldw rg0, rg2 0
stw rg0, spr 4
// push arg 0
push rg2
call print::print_num
pop zero
ldw spr, rg2 4
stw rg2, spr 4
addi spr, 4, rg3
ldw spr, rg2 8
stw rg2, spr 8
// push arg 1
push rg3
// push arg 0
push rg2
call alloc::free
pop zero
pop zero
ldw spr, rg2 8
stw rg2, spr 8
// push arg 0
push rg2
call alloc::alloc
pop rg3
push rg3
call print::print_newline
ldw spr, rg2 0
stw rg2, spr 0
// push arg 0
push rg2
call print::print_hex_word
pop zero
call print::print_newline
ldw spr, rg2 8
stw rg2, spr 8
// push arg 0
push rg2
call print::print_hex_word
pop zero
ldw spr, rg2 8
lli 0, rg4
cmp rg2, rg4
lli 1, rg5
jeq _cmp_end_1
lli 0, rg5
_cmp_end_1:
cmp rg5, zero
jeq _else_3
_then_2:
lwi str_5, rg4
stw rg2, spr 8
// push arg 0
push rg4
call print::print
pop zero
jmp _end_4
_else_3:
nop
_end_4:
lli 0, rg4
stw rg4, bpr 8
jmp _ret
resources/dsa/output.dsa
-214
View File
@@ -1,214 +0,0 @@
// GENERATED BY DSC COMPILER
// Generated at 2026-02-03 23:37:16
// Imports
include print: "./lib/io/print.dsa"
// Globals & Reserved Memory
dw heap_start: 196608
dw heap_end: 262144
dw heap_current: 196608
// Entry Point
dw stack: 0x10000
db message: "Process Exited with code:"
_init:
ldw stack, bpr
mov bpr, spr
push zero
call main
call print::print_newline
lwi message, rg0
push rg0
call print::print
pop zero
call print::print_hex_word
pop zero
hlt
// Return
_ret:
mov bpr, spr
pop bpr
return
// Compiled Code Starts...
main:
push bpr
mov spr, bpr
lli 0, rg0
push rg0 // bpr-4: x
subi bpr 4 rg1
lli 512, rg0
push rg1 // bpr-8: y
push rg0 // push arg 0
call arena_create
pop rg2
lli 32, rg0
push rg2 // bpr-12: alloc
push rg0 // push arg 1
push rg2 // push arg 0
call arena_alloc
pop rg3
pop zero
lli 32, rg0
subi bpr 12 rg2
ldw rg2, rg2 // bpr-20: alloc
push rg3 // bpr-16: ptr1
push rg2 // bpr-20: alloc
push rg0 // push arg 1
push rg2 // push arg 0
call arena_alloc
pop rg4
pop zero
subi bpr 20 rg0
ldw rg0, rg0 // bpr-28: alloc
push rg4 // bpr-24: ptr2
push rg0 // bpr-28: alloc
push rg0 // push arg 0
call print::print_hex_word
pop zero
call print::print_newline
subi bpr 16 rg0
ldw rg0, rg0 // bpr-24: ptr1
push rg0 // bpr-32: ptr1
push rg0 // push arg 0
call print::print_hex_word
pop zero
call print::print_newline
subi bpr 24 rg0
ldw rg0, rg0 // bpr-32: ptr2
push rg0 // bpr-36: ptr2
push rg0 // push arg 0
call print::print_hex_word
pop zero
call print::print_newline
subi bpr 36 rg0
ldw rg0, rg0 // bpr-44: ptr2
ldw rg0, rg2
push rg0 // bpr-40: ptr2
push rg2 // push arg 0
call print::print_num
pop zero
call print::print_newline
lli 42, rg2
subi bpr 40 rg5
ldw rg5, rg5 // bpr-48: ptr2
stw rg2, rg5
push rg5 // bpr-44: ptr2
push rg5 // push arg 0
call print::print_hex_word
pop zero
call print::print_newline
subi bpr 44 rg2
ldw rg2, rg2 // bpr-52: ptr2
ldw rg2, rg5
push rg2 // bpr-48: ptr2
push rg5 // push arg 0
call print::print_num
pop zero
call print::print_newline
db str_1: "end"
lwi str_1, rg5
push rg5 // push arg 0
call print::println
pop zero
lli 0, rg5
stw rg5, bpr, 8
jmp _ret
arena_create:
push bpr
mov spr, bpr
ldw bpr, rg0, 8
lli 12, rg1
add rg0, rg1, rg2
ldw heap_current, rg1
add rg1, rg2, rg3
ldw heap_end, rg4
cmp rg3, rg4
lli 0, rg5
jle _cmp_end_2
lli 1, rg5
_cmp_end_2:
cmp rg5, zero
jeq _else_4
_then_3:
lli 0, rg4
stw rg4, bpr, 8
jmp _ret
jmp _end_5
_else_4:
nop
_end_5:
lli 12, rg4
add rg1, rg4, rg5
add rg1, rg2, rg4
stw rg5, rg1
lli 4, rg6
add rg1, rg6, rg7
stw rg5, rg7
lli 8, rg6
add rg1, rg6, rg7
stw rg4, rg7
stw rg3, heap_current
stw rg1, bpr, 8
jmp _ret
arena_alloc:
push bpr
mov spr, bpr
ldw bpr, rg0, 8
ldw bpr, rg1, 12
lli 4, rg2
add rg0, rg2, rg3
ldw rg3, rg2
lli 8, rg3
add rg0, rg3, rg4
ldw rg4, rg3
add rg2, rg1, rg4
cmp rg4, rg3
lli 0, rg5
jle _cmp_end_6
lli 1, rg5
_cmp_end_6:
cmp rg5, zero
jeq _else_8
_then_7:
lli 0, rg5
stw rg5, bpr, 8
jmp _ret
jmp _end_9
_else_8:
nop
_end_9:
lli 4, rg5
add rg0, rg5, rg6
stw rg4, rg6
stw rg2, bpr, 8
jmp _ret
arena_destroy:
push bpr
mov spr, bpr
ldw bpr, rg0, 8
lli 0, rg1
stw rg1, bpr, 8
jmp _ret
reset_all:
push bpr
mov spr, bpr
ldw heap_start, rg0
stw rg0, heap_current
lli 0, rg0
stw rg0, bpr, 8
jmp _ret
resources/dsa/test.dsa
-50
View File
@@ -1,50 +0,0 @@
// GENERATED BY DSC COMPILER
// Generated at 2026-02-10 01:04:01
// Imports
include print: "./lib/io/print.dsa"
// Globals & Reserved Memory
// Entry Point
dw stack: 0x10000
db message: "Process Exited with code:"
_init:
ldw stack, bpr
mov bpr, spr
push zero
call main
call print::print_newline
lwi message, rg0
push rg0
call print::print
pop zero
call print::print_hex_word
pop zero
hlt
// Return
_ret:
mov bpr, spr
pop bpr
return
// Compiled Code Starts...
// fn main() -> u32
main:
push bpr
mov spr, bpr
lli 30, rg0
push rg0 // free var:x offset:-8
push rg0 // push arg 0
call print::print_num
pop zero
lli 200, rg0
lli 5, rg1
add rg0, rg1, rg2
jmp _ret
resources/dsa/testprint.dsa
+1 -1
View File
@@ -1,4 +1,4 @@
include print "./lib/io/print.dsa"
include print: "./lib/io/print.dsa"
dw idt: 0xFFFF0000
dw stack: 0x10000