CPU can now decode instructions, just waiting on the assembler

src/common/instructions.rs

@@ -1,6 +1,7 @@
 type Offset = u16;
 type Immediate = u16;
 
+#[derive(Copy, Clone, Debug, PartialEq)]
 pub enum Interrupt {
     Software(u8),
 }
@@ -23,6 +24,7 @@ impl From<u8> for Interrupt {
     }
 }
 
+#[derive(Copy, Clone, Debug, PartialEq)]
 pub enum Register {
     // general purpose registers
     Rg0,
@@ -129,6 +131,7 @@ impl std::fmt::Display for Register {
     }
 }
 
+#[derive(Debug, Clone)]
 pub enum Instruction {
     // No-op
     Nop,
@@ -142,7 +145,6 @@ pub enum Instruction {
     LoadHalfword(Register, Offset, Register),
     LoadHalfwordSigned(Register, Offset, Register),
     LoadWord(Register, Offset, Register),
-    LoadWordSigned(Register, Offset, Register),
 
     StoreByte(Register, Offset, Register),
     StoreHalfword(Register, Offset, Register),
@@ -168,8 +170,8 @@ pub enum Instruction {
     Sub(Register, Register, Register),
     Increment(Register),
     Decrement(Register),
-    ShiftLeft(Register, Register, Register),
-    ShiftRight(Register, Register, Register),
+    ShiftLeft(Register, Register, Immediate),
+    ShiftRight(Register, Register, Immediate),
 
     // Logical
     And(Register, Register, Register),
@@ -208,7 +210,6 @@ impl std::fmt::Display for Instruction {
             Instruction::LoadHalfword(a, b, c) => write!(f, "LDH {}, {}, {}", a, b, c),
             Instruction::LoadHalfwordSigned(a, b, c) => write!(f, "LDHS {}, {}, {}", a, b, c),
             Instruction::LoadWord(a, b, c) => write!(f, "LDW {}, {}, {}", a, b, c),
-            Instruction::LoadWordSigned(a, b, c) => write!(f, "LDWS {}, {}, {}", a, b, c),
 
             Instruction::StoreByte(a, b, c) => write!(f, "STB {}, {}, {}", a, b, c),
             Instruction::StoreHalfword(a, b, c) => write!(f, "STH {}, {}, {}", a, b, c),