working emulator UI - just need to implement the instruction set
This commit is contained in:
+187
-52
@@ -1,7 +1,138 @@
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type Offset = u16;
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type Immediate = u16;
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pub enum Interrupt {
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Software(u8),
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}
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pub type Address = u32;
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impl Interrupt {
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fn as_u8(&self) -> u8 {
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match self {
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Interrupt::Software(code) => *code,
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}
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}
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}
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impl From<u8> for Interrupt {
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fn from(_code: u8) -> Self {
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todo!("implement this once a hardware interrupt convention is established");
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#[allow(unreachable_code)]
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Interrupt::Software(_code)
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}
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}
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pub enum Register {
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// general purpose registers
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Rg0,
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Rg1,
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Rg2,
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Rg3,
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Rg4,
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Rg5,
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Rg6,
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Rg7,
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Rg8,
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Rg9,
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Rga,
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Rgb,
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Rgc,
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Rgd,
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Rge,
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Rgf,
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// special purpose registers
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Acc,
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Spr,
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Bpr,
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Ret,
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Idr,
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Mmr,
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Zero,
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None,
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// system registers - can't be written to by instructions.
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Mar,
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Mdr,
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Sts,
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Cir,
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Pcx,
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}
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impl From<u8> for Register {
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fn from(idx: u8) -> Register {
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match idx {
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// system registers are not indexable in the reg file so they cannot be modified by instructions.
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0x0 => Register::Rg0,
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0x1 => Register::Rg1,
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0x2 => Register::Rg2,
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0x3 => Register::Rg3,
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0x4 => Register::Rg4,
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0x5 => Register::Rg5,
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0x6 => Register::Rg6,
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0x7 => Register::Rg7,
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0x8 => Register::Rg8,
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0x9 => Register::Rg9,
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0xA => Register::Rga,
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0xB => Register::Rgb,
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0xC => Register::Rgc,
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0xD => Register::Rgd,
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0xE => Register::Rge,
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0xF => Register::Rgf,
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0x10 => Register::Acc,
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0x11 => Register::Spr,
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0x12 => Register::Bpr,
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0x13 => Register::Ret,
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0x14 => Register::Idr,
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0x15 => Register::Mmr,
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0x16 => Register::Zero,
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0x17 => Register::None,
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_ => panic!("invalid register"),
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}
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}
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}
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impl std::fmt::Display for Register {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match self {
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Register::Rg0 => write!(f, "Rg0"),
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Register::Rg1 => write!(f, "Rg1"),
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Register::Rg2 => write!(f, "Rg2"),
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Register::Rg3 => write!(f, "Rg3"),
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Register::Rg4 => write!(f, "Rg4"),
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Register::Rg5 => write!(f, "Rg5"),
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Register::Rg6 => write!(f, "Rg6"),
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Register::Rg7 => write!(f, "Rg7"),
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Register::Rg8 => write!(f, "Rg8"),
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Register::Rg9 => write!(f, "Rg9"),
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Register::Rga => write!(f, "Rga"),
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Register::Rgb => write!(f, "Rgb"),
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Register::Rgc => write!(f, "Rgc"),
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Register::Rgd => write!(f, "Rgd"),
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Register::Rge => write!(f, "Rge"),
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Register::Rgf => write!(f, "Rgf"),
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Register::Acc => write!(f, "Acc"),
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Register::Spr => write!(f, "Spr"),
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Register::Bpr => write!(f, "Bpr"),
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Register::Ret => write!(f, "Ret"),
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Register::Idr => write!(f, "Idr"),
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Register::Mmr => write!(f, "Mmr"),
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Register::Zero => write!(f, "Zero"),
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Register::None => write!(f, "None"),
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Register::Mar => write!(f, "Mar"),
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Register::Mdr => write!(f, "Mdr"),
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Register::Sts => write!(f, "Sts"),
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Register::Cir => write!(f, "Cir"),
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Register::Pcx => write!(f, "Pcx"),
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}
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}
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}
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pub enum Instruction {
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// No-op
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Nop,
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// Data transfer instructions
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Mov(Register, Register),
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MovSigned(Register, Register),
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@@ -55,61 +186,65 @@ pub enum Instruction {
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Halt,
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}
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type Offset = u16;
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type Immediate = u16;
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impl Instruction {
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pub fn encode(&self) -> u32 {
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todo!("imlement instruction encoding")
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}
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pub enum Interrupt {
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Software(u8)
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pub fn decode(data: u32) -> Self {
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// TODO: this needs to actually decode something
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Instruction::Nop
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}
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}
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impl Into<u8> for Interrupt {
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fn into(self) -> u8 {
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impl std::fmt::Display for Instruction {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match self {
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Interrupt::Software(code) => code,
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Instruction::Nop => write!(f, "No Operation"),
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Instruction::Mov(a, b) => write!(f, "MOV {}, {}", a, b),
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Instruction::MovSigned(a, b) => write!(f, "MOVS {}, {}", a, b),
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Instruction::LoadByte(a, b, c) => write!(f, "LDB {}, {}, {}", a, b, c),
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Instruction::LoadByteSigned(a, b, c) => write!(f, "LDBS {}, {}, {}", a, b, c),
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Instruction::LoadHalfword(a, b, c) => write!(f, "LDH {}, {}, {}", a, b, c),
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Instruction::LoadHalfwordSigned(a, b, c) => write!(f, "LDHS {}, {}, {}", a, b, c),
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Instruction::LoadWord(a, b, c) => write!(f, "LDW {}, {}, {}", a, b, c),
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Instruction::LoadWordSigned(a, b, c) => write!(f, "LDWS {}, {}, {}", a, b, c),
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Instruction::StoreByte(a, b, c) => write!(f, "STB {}, {}, {}", a, b, c),
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Instruction::StoreHalfword(a, b, c) => write!(f, "STH {}, {}, {}", a, b, c),
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Instruction::StoreWord(a, b, c) => write!(f, "STW {}, {}, {}", a, b, c),
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Instruction::LoadLowerImmediate(a, b) => write!(f, "LLI {}, {}", a, b),
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Instruction::LoadUpperImmediate(a, b) => write!(f, "LUI {}, {}", a, b),
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Instruction::Jump(a, b) => write!(f, "JMP {}, {}", a, b),
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Instruction::JumpEq(a, b) => write!(f, "JEQ {}, {}", a, b),
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Instruction::JumpNeq(a, b) => write!(f, "JNEQ {}, {}", a, b),
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Instruction::JumpGt(a, b) => write!(f, "JGT {}, {}", a, b),
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Instruction::JumpGe(a, b) => write!(f, "JGE {}, {}", a, b),
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Instruction::JumpLt(a, b) => write!(f, "JLT {}, {}", a, b),
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Instruction::JumpLe(a, b) => write!(f, "JLE {}, {}", a, b),
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Instruction::Compare(a, b) => write!(f, "CMP {}, {}", a, b),
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Instruction::Add(a, b, c) => write!(f, "ADD {}, {}, {}", a, b, c),
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Instruction::Sub(a, b, c) => write!(f, "SUB {}, {}, {}", a, b, c),
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Instruction::Increment(a) => write!(f, "INC {}", a),
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Instruction::Decrement(a) => write!(f, "DEC {}", a),
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Instruction::ShiftLeft(a, b, c) => write!(f, "SHL {}, {}, {}", a, b, c),
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Instruction::ShiftRight(a, b, c) => write!(f, "SHR {}, {}, {}", a, b, c),
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Instruction::And(a, b, c) => write!(f, "AND {}, {}, {}", a, b, c),
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Instruction::Or(a, b, c) => write!(f, "OR {}, {}, {}", a, b, c),
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Instruction::Not(a, b) => write!(f, "NOT {}, {}", a, b),
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Instruction::Xor(a, b, c) => write!(f, "XOR {}, {}, {}", a, b, c),
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Instruction::Nand(a, b, c) => write!(f, "NAND {}, {}, {}", a, b, c),
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Instruction::Nor(a, b, c) => write!(f, "NOR {}, {}, {}", a, b, c),
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Instruction::Xnor(a, b, c) => write!(f, "XNOR {}, {}, {}", a, b, c),
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Instruction::Interrupt(a) => write!(f, "INT {}", a.as_u8()),
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Instruction::IntReturn => write!(f, "INTR"),
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Instruction::Halt => write!(f, "HALT"),
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}
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}
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}
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impl From<u8> for Interrupt {
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fn from(code: u8) -> Self {
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todo!("implement this once a hardware interrupt convention is established");
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Interrupt::Software(code)
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}
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}
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pub enum Register {
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// general purpose registers
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Rg0,
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Rg1,
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Rg2,
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Rg3,
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Rg4,
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Rg5,
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Rg6,
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Rg7,
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Rg8,
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Rg9,
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Rg10,
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Rg11,
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Rg12,
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Rg13,
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Rg14,
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Rg15,
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// special purpose registers
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Acc,
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Spr,
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Bpr,
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Ret,
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Idr,
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Mmr,
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Zero,
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None,
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// system registers - can't be written to by instructions.
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Mar,
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Mdr,
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Sts,
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Cir,
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Pcx,
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}
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