use serde::{Deserialize, Serialize};

use crate::memory::mmu::MMU;

mod cache;
pub mod mainstore;
pub mod mmu;
mod tlb;

pub type VirtAddr = u32;
pub type PhysAddr = u32;

pub enum FaultInfo {
    PageFault,
}

#[repr(u32)]
#[derive(Serialize, Deserialize, Clone, Copy)]
enum RegionType {
    Reserved,
    Bootloader,
    Kernel,
    KernelTables,
    Usable,
    MMIO,
}

#[derive(Serialize, Deserialize, Clone, Copy)]
pub struct Region {
    base: PhysAddr,
    size: usize,
    region_type: RegionType,
}

#[derive(Serialize, Deserialize)]
pub struct MemoryMap {
    table_addr: PhysAddr,
    pub regions: Vec<Region>,
}

impl MemoryMap {
    pub const DEFAULT_MEMORY_MAP_ADDR: PhysAddr = 0x1000;

    pub fn new() -> Self {
        MemoryMap {
            table_addr: Self::DEFAULT_MEMORY_MAP_ADDR,
            regions: Vec::new(),
        }
    }

    pub fn identity_map(mmu: &mut MMU, region: &Region) {
        let first_page = region.base >> 12;
        let page_count = (region.size >> 12) as u32;

        for page in (first_page..first_page + page_count).map(|p| p << 12) {
            mmu.create_mapping(page, page);
        }
    }
}

impl Default for MemoryMap {
    fn default() -> Self {
        ron::from_str(include_str!("../../config/dsa.mmap.ron")).unwrap()
    }
}