started assembler logic rewrite

This commit is contained in:
2026-03-13 16:39:58 +00:00
parent 6da473c272
commit 06c6ba534d
15 changed files with 359 additions and 27 deletions
+6 -9
View File
@@ -1,26 +1,23 @@
use std::{
hint::unlikely,
ops::{Add, AddAssign},
ops::AddAssign,
sync::{
Arc,
atomic::Ordering,
mpsc::{self, TryRecvError},
Arc,
},
thread,
time::{Duration, Instant},
};
use common::{
instructions::{Instruction, Opcode},
register::Register,
};
use common::isa::instructions::{Instruction, Opcode};
use common::isa::register::Register;
use crate::{
Page,
config::{IoMapping, MemoryMap, RegionType},
io::{IoAccess, IoDevice, MappedDevice},
io::{IoDevice, MappedDevice},
memory::{mmu::MMU, ram::RandomAccessMemory},
processor::{interrupts::Interrupt, state::SharedState},
Page,
};
pub struct Emulator<Mem: RandomAccessMemory> {