started assembler logic rewrite

dsa/common/src/asm/asm_opcode.rs

@@ -0,0 +1,67 @@
+pub enum AsmOpcode {
+    Nop,
+
+    // move
+    Mov,
+    CMov,
+
+    // load
+    Ldb,
+    Ldbs,
+    Ldh,
+    Ldhs,
+    Ldw,
+
+    // store
+    Stb,
+    Sth,
+    Stw,
+
+    // load immediate
+    Lli,
+    Lui,
+    Lwi,
+
+    // comparison
+    Ieq,
+    Ine,
+    Ilt,
+    Ile,
+    Igt,
+    Ige,
+
+    // jump
+    Jmp,
+    Jez,
+    Jnz,
+    Jic,
+    Jnc,
+
+    // bitwise
+    And,
+    Nand,
+    Or,
+    Nor,
+    Xor,
+    Xnor,
+    Not,
+
+    // arithmetic
+    Add,
+    Sub,
+    Shl,
+    Shr,
+    Addi,
+    Subi,
+
+    // utility
+    Push,
+    Pop,
+    Call,
+    Ret,
+
+    // system
+    Int,
+    IRet,
+    Hlt,
+}

dsa/common/src/asm/mod.rs

@@ -0,0 +1,232 @@
+use crate::prelude::Register;
+
+pub struct Location {
+    offset: u16,
+    register: Option<Register>,
+    label: Option<String>,
+}
+
+impl Location {
+    pub fn new(offset: u16, register: Option<Register>, label: Option<String>) -> Self {
+        Location {
+            offset,
+            register,
+            label,
+        }
+    }
+
+    // need implementation to intelligently figure out if we need to load immediates
+    // so if the label is a const and > u16::max, we do Lui $label temp, then use temp as an offset
+    // if a register is being used already we have to add the offset to that.
+}
+
+pub enum ImmConst {
+    Label(String),
+    Imm16(u16),
+    Imm32(u32),
+}
+
+pub enum PseudoInstruction {
+    Nop,
+
+    // move
+    Mov {
+        src: Register,
+        dest: Register,
+    },
+    CMov {
+        src: Register,
+        dest: Register,
+        condition: Register,
+    },
+
+    // load
+    Ldb {
+        addr: Location,
+        dest: Register,
+    },
+    Ldbs {
+        addr: Location,
+        dest: Register,
+    },
+    Ldh {
+        addr: Location,
+        dest: Register,
+    },
+    Ldhs {
+        addr: Location,
+        dest: Register,
+    },
+    Ldw {
+        addr: Location,
+        dest: Register,
+    },
+
+    // store
+    Stb {
+        src: Register,
+        addr: Location,
+    },
+    Sth {
+        src: Register,
+        addr: Location,
+    },
+    Stw {
+        src: Register,
+        addr: Location,
+    },
+
+    // load immediate
+    Lli {
+        dest: Register,
+        value: ImmConst,
+    },
+    Lui {
+        dest: Register,
+        value: ImmConst,
+    },
+    Lwi {
+        dest: Register,
+        value: ImmConst,
+    },
+
+    // comparison
+    Ieq {
+        src1: Register,
+        src2: Register,
+        dest: Register,
+    },
+    Ine {
+        src1: Register,
+        src2: Register,
+        dest: Register,
+    },
+    Ilt {
+        src1: Register,
+        src2: Register,
+        dest: Register,
+    },
+    Ile {
+        src1: Register,
+        src2: Register,
+        dest: Register,
+    },
+    Igt {
+        src1: Register,
+        src2: Register,
+        dest: Register,
+    },
+    Ige {
+        src1: Register,
+        src2: Register,
+        dest: Register,
+    },
+
+    // jump
+    Jmp {
+        dest: Location,
+    },
+    Jez {
+        dest: Location,
+        cond: Register,
+    },
+    Jnz {
+        dest: Location,
+        cond: Register,
+    },
+    Jic {
+        dest: Location,
+    },
+    Jnc {
+        dest: Location,
+    },
+
+    // bitwise
+    And {
+        src1: Register,
+        src2: Register,
+        dest: Option<Register>,
+    },
+    Nand {
+        src1: Register,
+        src2: Register,
+        dest: Option<Register>,
+    },
+    Or {
+        src1: Register,
+        src2: Register,
+        dest: Option<Register>,
+    },
+    Nor {
+        src1: Register,
+        src2: Register,
+        dest: Register,
+    },
+    Xor {
+        src1: Register,
+        src2: Register,
+        dest: Option<Register>,
+    },
+    Xnor {
+        src1: Register,
+        src2: Register,
+        dest: Option<Register>,
+    },
+    Not {
+        src: Register,
+        dest: Option<Register>,
+    },
+
+    // arithmetic
+    Add {
+        src1: Register,
+        src2: Register,
+        dest: Option<Register>,
+    },
+    Sub {
+        src1: Register,
+        src2: Register,
+        dest: Option<Register>,
+    },
+    Shl {
+        src: Register,
+        shamt_r: Option<Register>,
+        shamt_i: Option<ImmConst>,
+        dest: Option<Register>,
+    },
+    Shr {
+        src: Register,
+        shamt_r: Option<Register>,
+        shamt_i: Option<ImmConst>,
+        dest: Option<Register>,
+    },
+    Addi {
+        src: Register,
+        value: ImmConst,
+        dest: Option<Register>,
+    },
+    Subi {
+        src: Register,
+        value: ImmConst,
+        dest: Option<Register>,
+    },
+
+    // utility
+    Push {
+        src: Register,
+    },
+    Pop {
+        dest: Register,
+    },
+    Call {
+        dest: Location,
+    },
+    Ret,
+
+    // system
+    Int {
+        code: ImmConst,
+    },
+    IRet,
+    Hlt,
+}

dsa/common/src/isa/instructions/decode.rs

@@ -1,4 +1,5 @@
-use crate::{instructions::Instruction, register::Register};
+use crate::isa::instructions::Instruction;
+use crate::isa::register::Register;
 
 impl Instruction {
     #[inline]

dsa/common/src/isa/instructions/encode.rs

@@ -1,9 +1,7 @@
 use std::ops::{Deref, DerefMut};
 
-use crate::{
-    instructions::{Instruction, Opcode},
-    register::Register,
-};
+use crate::isa::instructions::{Instruction, Opcode};
+use crate::isa::register::Register;
 
 impl From<u32> for Instruction {
     #[inline]

dsa/common/src/isa/mod.rs

@@ -0,0 +1,2 @@
+pub mod register;
+pub mod instructions;

dsa/common/src/lib.rs

@@ -1,7 +1,7 @@
-pub mod instructions;
-pub mod register;
+pub mod asm;
+pub mod isa;
 
 pub mod prelude {
-    pub use crate::instructions::Instruction;
-    pub use crate::register::Register;
+    pub use crate::isa::instructions::Instruction;
+    pub use crate::isa::register::Register;
 }

dsa/emulator/src/bin/bench_emu.rs

@@ -1,4 +1,4 @@
-use common::instructions::Instruction;
+use common::isa::instructions::Instruction;
 use dsa::{BulkAllocStore, Emulator, Page, RandomAccessMemory};
 /// DSA Emulator Benchmark
 ///

dsa/emulator/src/main.rs

@@ -1,18 +1,15 @@
 use clap::Parser;
-use common::{instructions::Instruction, register::Register};
+use common::isa::instructions::Instruction;
 use dsa::{
-    BulkAllocStore, Emulator, Page, RandomAccessMemory, SharedState,
-    args::DsaArgs,
-    io::display::{DisplayDevice, DisplayHandle},
+    args::DsaArgs, io::display::{DisplayDevice, DisplayHandle}, BulkAllocStore, Emulator, Page,
+    RandomAccessMemory,
+    SharedState,
 };
 use std::{
-    os::unix::thread::JoinHandleExt,
-    process::exit,
-    sync::{Arc, atomic::Ordering},
+    sync::{atomic::Ordering, Arc},
     thread,
     time::Duration,
 };
-
 fn main() {
     let args = DsaArgs::parse();
 

dsa/emulator/src/processor/processor.rs

@@ -1,26 +1,23 @@
 use std::{
     hint::unlikely,
-    ops::{Add, AddAssign},
+    ops::AddAssign,
     sync::{
-        Arc,
         atomic::Ordering,
         mpsc::{self, TryRecvError},
+        Arc,
     },
     thread,
     time::{Duration, Instant},
 };
 
-use common::{
-    instructions::{Instruction, Opcode},
-    register::Register,
-};
-
+use common::isa::instructions::{Instruction, Opcode};
+use common::isa::register::Register;
 use crate::{
-    Page,
     config::{IoMapping, MemoryMap, RegionType},
-    io::{IoAccess, IoDevice, MappedDevice},
+    io::{IoDevice, MappedDevice},
     memory::{mmu::MMU, ram::RandomAccessMemory},
     processor::{interrupts::Interrupt, state::SharedState},
+    Page,
 };
 
 pub struct Emulator<Mem: RandomAccessMemory> {