101 lines
3.0 KiB
Rust
101 lines
3.0 KiB
Rust
#![expect(unused)]
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use core::arch::x86_64::__cpuid;
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use crate::arch::x86_64::cpu::msr::*;
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use crate::arch::x86_64::memory::mapping::PHYSICAL_MEMORY_OFFSET;
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use crate::arch::x86_64::memory::{FRAME_ALLOCATOR, OFFSET_PAGE_TABLE};
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use crate::{debugln, serial_print, serial_println};
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use x86_64::structures::paging::Translate;
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use x86_64::{
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PhysAddr, VirtAddr,
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structures::paging::{Mapper, Page, PageTableFlags, PhysFrame, Size4KiB},
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};
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const IA32_APIC_BASE_MSR: u32 = 0x1b;
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const IA32_APIC_BASE_MSR_BSP: u64 = 0x100;
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const IA32_APIC_BASE_MSR_ENABLE: u64 = 0x800;
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const IA32_APIC_BASE_MSR_DISABLE: u64 = !IA32_APIC_BASE_MSR_ENABLE;
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const CPUID_FEAT_EDX_APIC: u64 = 1 << 9; // the cpuid instruction will return this flag if it supports APIC
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// const APIC_VIRTUAL_ADDRESS: Lazy<VirtAddr> = Lazy::new(|| {
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// let apic_base = get_apic_base();
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// let virt_addr = unsafe { phys_to_virt(apic_base) };
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// virt_addr
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// });
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fn set_apic_base_enable(apic: PhysAddr) {
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let rax = (apic.as_u64() & 0xfffff0000) | IA32_APIC_BASE_MSR_ENABLE;
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debugln!("apic {:?}", PhysAddr::new(rax));
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cpu_set_msr(IA32_APIC_BASE_MSR, rax);
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}
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#[allow(dead_code)]
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fn set_apic_base_disable(apic: PhysAddr) {
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let rax = (apic.as_u64() & 0xfffff0000) & IA32_APIC_BASE_MSR_DISABLE;
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cpu_set_msr(IA32_APIC_BASE_MSR, rax);
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}
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fn get_apic_base() -> PhysAddr {
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let mut value: u64 = 0;
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cpu_get_msr(IA32_APIC_BASE_MSR, &mut value);
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debugln!("apic base {:#x}", value);
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PhysAddr::new(value & 0xfffff0000)
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}
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fn write_apic_register(apic_base: &PhysAddr, reg: u64, value: u32) {
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let apic_base = apic_base.as_u64();
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let reg_addr = (apic_base & 0xFFFFF0000) + reg;
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let virt_addr = unsafe { phys_to_virt(PhysAddr::new(reg_addr)) };
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let phys_check =
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OFFSET_PAGE_TABLE.get().unwrap().lock().translate(virt_addr);
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debugln!("{:?}", phys_check);
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unsafe { *(virt_addr.as_u64() as *mut u32) = value };
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}
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fn read_apic_register(apic_base: &PhysAddr, reg: u64) -> u32 {
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let apic_base = apic_base.as_u64();
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let reg_addr = (apic_base & 0xFFFFF0000) + reg;
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let virt_addr = unsafe { phys_to_virt(PhysAddr::new(reg_addr)) };
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unsafe { *(virt_addr.as_u64() as *const u32) }
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}
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pub fn check_apic() -> bool {
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let res = unsafe { __cpuid(1) };
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res.edx as u64 & CPUID_FEAT_EDX_APIC != 0
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}
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#[inline(always)]
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unsafe fn phys_to_virt(phys: PhysAddr) -> VirtAddr {
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let phys = phys.as_u64();
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phys.checked_add(*PHYSICAL_MEMORY_OFFSET)
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.map_or_else(|| panic!(" overflow"), VirtAddr::new)
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}
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pub fn enable_apic() {
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let apic_base_physical_addr = get_apic_base();
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set_apic_base_enable(apic_base_physical_addr);
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debugln!("{:?}", apic_base_physical_addr);
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enable_timer();
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write_apic_register(
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&apic_base_physical_addr,
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0xF0,
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read_apic_register(&apic_base_physical_addr, 0xF0) | 0x1FF,
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);
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}
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pub fn enable_timer() {
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let apic_base = get_apic_base();
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let current = read_apic_register(&apic_base, 0x320);
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write_apic_register(&get_apic_base(), 0x320, (current & 0xFFFFFF00) | 0x20);
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}
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