#![expect(unused)]

use core::arch::x86_64::__cpuid;

use crate::arch::x86_64::cpu::msr::*;
use crate::arch::x86_64::memory::mapping::PHYSICAL_MEMORY_OFFSET;
use crate::arch::x86_64::memory::{FRAME_ALLOCATOR, OFFSET_PAGE_TABLE};
use crate::{debugln, serial_print, serial_println};
use x86_64::structures::paging::Translate;
use x86_64::{
    PhysAddr, VirtAddr,
    structures::paging::{Mapper, Page, PageTableFlags, PhysFrame, Size4KiB},
};

const IA32_APIC_BASE_MSR: u32 = 0x1b;
const IA32_APIC_BASE_MSR_BSP: u64 = 0x100;
const IA32_APIC_BASE_MSR_ENABLE: u64 = 0x800;
const IA32_APIC_BASE_MSR_DISABLE: u64 = !IA32_APIC_BASE_MSR_ENABLE;

const CPUID_FEAT_EDX_APIC: u64 = 1 << 9; // the cpuid instruction will return this flag if it supports APIC

// const APIC_VIRTUAL_ADDRESS: Lazy<VirtAddr> = Lazy::new(|| {
//     let apic_base = get_apic_base();
//     let virt_addr = unsafe { phys_to_virt(apic_base) };

//     virt_addr
// });

fn set_apic_base_enable(apic: PhysAddr) {
    let rax = (apic.as_u64() & 0xfffff0000) | IA32_APIC_BASE_MSR_ENABLE;
    debugln!("apic {:?}", PhysAddr::new(rax));
    cpu_set_msr(IA32_APIC_BASE_MSR, rax);
}

#[allow(dead_code)]
fn set_apic_base_disable(apic: PhysAddr) {
    let rax = (apic.as_u64() & 0xfffff0000) & IA32_APIC_BASE_MSR_DISABLE;
    cpu_set_msr(IA32_APIC_BASE_MSR, rax);
}

fn get_apic_base() -> PhysAddr {
    let mut value: u64 = 0;
    cpu_get_msr(IA32_APIC_BASE_MSR, &mut value);

    debugln!("apic base {:#x}", value);

    PhysAddr::new(value & 0xfffff0000)
}

fn write_apic_register(apic_base: &PhysAddr, reg: u64, value: u32) {
    let apic_base = apic_base.as_u64();
    let reg_addr = (apic_base & 0xFFFFF0000) + reg;

    let virt_addr = unsafe { phys_to_virt(PhysAddr::new(reg_addr)) };

    let phys_check =
        OFFSET_PAGE_TABLE.get().unwrap().lock().translate(virt_addr);
    debugln!("{:?}", phys_check);

    unsafe { *(virt_addr.as_u64() as *mut u32) = value };
}

fn read_apic_register(apic_base: &PhysAddr, reg: u64) -> u32 {
    let apic_base = apic_base.as_u64();
    let reg_addr = (apic_base & 0xFFFFF0000) + reg;
    let virt_addr = unsafe { phys_to_virt(PhysAddr::new(reg_addr)) };
    unsafe { *(virt_addr.as_u64() as *const u32) }
}

pub fn check_apic() -> bool {
    let res = unsafe { __cpuid(1) };
    res.edx as u64 & CPUID_FEAT_EDX_APIC != 0
}

#[inline(always)]
unsafe fn phys_to_virt(phys: PhysAddr) -> VirtAddr {
    let phys = phys.as_u64();
    phys.checked_add(*PHYSICAL_MEMORY_OFFSET)
        .map_or_else(|| panic!(" overflow"), VirtAddr::new)
}

pub fn enable_apic() {
    let apic_base_physical_addr = get_apic_base();
    set_apic_base_enable(apic_base_physical_addr);

    debugln!("{:?}", apic_base_physical_addr);
    enable_timer();

    write_apic_register(
        &apic_base_physical_addr,
        0xF0,
        read_apic_register(&apic_base_physical_addr, 0xF0) | 0x1FF,
    );
}

pub fn enable_timer() {
    let apic_base = get_apic_base();
    let current = read_apic_register(&apic_base, 0x320);
    write_apic_register(&get_apic_base(), 0x320, (current & 0xFFFFFF00) | 0x20);
}